From patchwork Tue May 5 13:50:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjun Guo X-Patchwork-Id: 6338401 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4464EBEEE1 for ; Tue, 5 May 2015 13:56:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4321420259 for ; Tue, 5 May 2015 13:56:10 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 43F122017D for ; Tue, 5 May 2015 13:56:09 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YpdHk-0003nP-Ho; Tue, 05 May 2015 13:53:20 +0000 Received: from mail-pd0-f177.google.com ([209.85.192.177]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YpdHM-0003Pz-Ol for linux-arm-kernel@lists.infradead.org; Tue, 05 May 2015 13:52:57 +0000 Received: by pdbqa5 with SMTP id qa5so196558833pdb.1 for ; Tue, 05 May 2015 06:52:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8M/U0bet+XkgrD1ObUf5A7T13Z4fBh/pfO9OoAsXTTY=; b=OsehcUvDA9XFvjnV0dPtCnmOoEQOV592bSxLh9BnPihaimhTzGVaBLoPr2eGl0vf6+ KgLsRGrHlLwc4QzUVva3QckrI4my2G3kxjM8/3NP/nva/l2xLyGZSKU/OJI0inHP+hlX SGjWyP0sh/wcCEuMSdWgz0XjWwN8bQ25tk6KhMecGuyi1iMJveGokYa/c2bC4X7AsK3i vHAlgKHp9wXxCayJ1J2r7GwkP5/YnUd45Diz8Evh8/hoGL3W40pqJDYT1SaCJxS0NtAg WvubUsBxKpkOZTea+JE2Qaq7g8JEU8ty/tGOoY+SojwpmZL17MRt+LedioH+sdIFzKhi phyA== X-Gm-Message-State: ALoCoQmy1Zk5BfeJXCilQAbK+CFwBw2yicNZHfWXSOBkrpAxlwEArx6oiWuP5lh3tBhCdfVhFr/i X-Received: by 10.68.108.65 with SMTP id hi1mr51390358pbb.129.1430833955490; Tue, 05 May 2015 06:52:35 -0700 (PDT) Received: from localhost ([180.150.157.4]) by mx.google.com with ESMTPSA id en2sm16176028pab.14.2015.05.05.06.52.32 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 05 May 2015 06:52:33 -0700 (PDT) From: Hanjun Guo To: Marc Zyngier , Jason Cooper , Will Deacon , Catalin Marinas , "Rafael J. Wysocki" Subject: [RFC PATCH 4/9] irqchip: gic: ACPI: Use IRQCHIP_ACPI_DECLARE to simplify GICv2 init code Date: Tue, 5 May 2015 21:50:52 +0800 Message-Id: <1430833857-30736-5-git-send-email-hanjun.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430833857-30736-1-git-send-email-hanjun.guo@linaro.org> References: <1430833857-30736-1-git-send-email-hanjun.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150505_065256_847697_C871532D X-CRM114-Status: GOOD ( 13.33 ) X-Spam-Score: -0.7 (/) Cc: Lorenzo Pieralisi , Arnd Bergmann , linux-acpi@vger.kernel.org, linaro-acpi@lists.linaro.org, linux-kernel@vger.kernel.org, Tomasz Nowicki , Olof Johansson , Hanjun Guo , Grant Likely , Thomas Gleixner , Jiang Liu , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As the ACPI self-probe infrastructure for irqchip is ready, we use the infrastructure and the GIC version to simplify GICv2 init code. From now on, GIC init calls reside in theirs drivers only. This means the code becomes cleaner and it is not spread outside irqchip driver. Signed-off-by: Hanjun Guo --- arch/arm64/include/asm/irq.h | 13 ------------- arch/arm64/kernel/acpi.c | 25 ------------------------- drivers/acpi/irq.c | 2 +- drivers/irqchip/irq-gic-acpi.c | 5 +++++ drivers/irqchip/irq-gic.c | 6 +++++- include/linux/acpi_irq.h | 4 +++- include/linux/irqchip/arm-gic-acpi.h | 10 ++-------- 7 files changed, 16 insertions(+), 49 deletions(-) diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h index bbb251b..94c5367 100644 --- a/arch/arm64/include/asm/irq.h +++ b/arch/arm64/include/asm/irq.h @@ -1,8 +1,6 @@ #ifndef __ASM_IRQ_H #define __ASM_IRQ_H -#include - #include struct pt_regs; @@ -10,15 +8,4 @@ struct pt_regs; extern void migrate_irqs(void); extern void set_handle_irq(void (*handle_irq)(struct pt_regs *)); -static inline void acpi_irq_init(void) -{ - /* - * Hardcode ACPI IRQ chip initialization to GICv2 for now. - * Proper irqchip infrastructure will be implemented along with - * incoming GICv2m|GICv3|ITS bits. - */ - acpi_gic_init(); -} -#define acpi_irq_init acpi_irq_init - #endif diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c index 8b83955..69809e7 100644 --- a/arch/arm64/kernel/acpi.c +++ b/arch/arm64/kernel/acpi.c @@ -318,28 +318,3 @@ void __init acpi_boot_table_init(void) disable_acpi(); } } - -void __init acpi_gic_init(void) -{ - struct acpi_table_header *table; - acpi_status status; - acpi_size tbl_size; - int err; - - if (acpi_disabled) - return; - - status = acpi_get_table_with_size(ACPI_SIG_MADT, 0, &table, &tbl_size); - if (ACPI_FAILURE(status)) { - const char *msg = acpi_format_exception(status); - - pr_err("Failed to get MADT table, %s\n", msg); - return; - } - - err = gic_v2_acpi_init(table); - if (err) - pr_err("Failed to initialize GIC IRQ controller"); - - early_acpi_os_unmap_memory((char *)table, tbl_size); -} diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c index 855ead9..7bd1ef6 100644 --- a/drivers/acpi/irq.c +++ b/drivers/acpi/irq.c @@ -25,7 +25,7 @@ irqchip_acpi_match_end __used __section(__irqchip_acpi_table_end); extern struct acpi_table_id __irqchip_acpi_table[]; -void __init acpi_irqchip_init(void) +void __init acpi_irq_init(void) { struct acpi_table_id *id; diff --git a/drivers/irqchip/irq-gic-acpi.c b/drivers/irqchip/irq-gic-acpi.c index 4796f07..7172ff1 100644 --- a/drivers/irqchip/irq-gic-acpi.c +++ b/drivers/irqchip/irq-gic-acpi.c @@ -21,6 +21,11 @@ static u8 gic_version __initdata = ACPI_MADT_GIC_VER_UNKNOWN; static phys_addr_t dist_phy_base __initdata; +u8 __init acpi_gic_version(void) +{ + return gic_version; +} + static int __init acpi_gic_parse_distributor(struct acpi_subtable_header *header, const unsigned long end) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 7b315e3..476dc7b 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -1154,12 +1154,15 @@ gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, return 0; } -int __init +static int __init gic_v2_acpi_init(struct acpi_table_header *table) { void __iomem *cpu_base, *dist_base; int count; + if (acpi_gic_version() >= ACPI_MADT_GIC_VER_V3) + return -ENODEV; + /* Collect CPU base addresses */ count = acpi_parse_entries(ACPI_SIG_MADT, sizeof(struct acpi_table_madt), @@ -1210,4 +1213,5 @@ gic_v2_acpi_init(struct acpi_table_header *table) acpi_irq_model = ACPI_IRQ_MODEL_GIC; return 0; } +IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_SIG_MADT, gic_v2_acpi_init); #endif diff --git a/include/linux/acpi_irq.h b/include/linux/acpi_irq.h index f10c872..4c0e108 100644 --- a/include/linux/acpi_irq.h +++ b/include/linux/acpi_irq.h @@ -3,7 +3,9 @@ #include -#ifndef acpi_irq_init +#ifdef CONFIG_ACPI +void acpi_irq_init(void); +#else static inline void acpi_irq_init(void) { } #endif diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h index 0d5f204..021e8e8 100644 --- a/include/linux/irqchip/arm-gic-acpi.h +++ b/include/linux/irqchip/arm-gic-acpi.h @@ -21,13 +21,7 @@ #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) -struct acpi_table_header; - -int gic_v2_acpi_init(struct acpi_table_header *table); -void acpi_gic_init(void); int acpi_gic_version_init(void); -#else -static inline void acpi_gic_init(void) { } -#endif - +u8 acpi_gic_version(void); +#endif /* CONFIG_ACPI */ #endif /* ARM_GIC_ACPI_H_ */