From patchwork Tue May 5 13:50:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjun Guo X-Patchwork-Id: 6338411 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 52D0B9F32B for ; Tue, 5 May 2015 13:57:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5F7E320251 for ; Tue, 5 May 2015 13:57:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6D0A02017D for ; Tue, 5 May 2015 13:56:59 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YpdIA-00042G-Tc; Tue, 05 May 2015 13:53:46 +0000 Received: from mail-pa0-f54.google.com ([209.85.220.54]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YpdHV-0003UG-Ed for linux-arm-kernel@lists.infradead.org; Tue, 05 May 2015 13:53:06 +0000 Received: by pabtp1 with SMTP id tp1so193957275pab.2 for ; Tue, 05 May 2015 06:52:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Me9tZo8vfmTRqkZwrbZx/XUdtd2RKgGqUdpotIvk+qU=; b=eebEOwnZcZCSD4Qvv06vfjF8rE3XyuFGdlImjitdVlydMEDpzB8B/iE1kwxouAJ/eK Pavw6uo0hOim3rhotaO4xtWw2D2I7DRQ6m+2uJaoyIhiZT5y+3vnMjEUeGYoTtF7g66C tb/G5UZ2JVvxaOJzA1oQwCj/9IxuY0jaMAQPUqEQN9A1dyvhIP+P6j9D8llktvzDVmto bTemdVTXhFHV4isXzEMnO+1yvjol+Gkn4V2WsyhcHCGnb0kgOa/urRTsQ3se+hrqioxW CW7uSESBLhUadhQgzrIJVWmdsT7huaPAOZlcB64n2yBRceloLqAoTIUzB9fQbP6eTj/i yMiw== X-Gm-Message-State: ALoCoQknrzorYZITYUYIQ2kEo9veSgVssY2u1lX63JPoltbc6bLuFvDU/MdQetjPxD6+96UcD5nJ X-Received: by 10.68.131.225 with SMTP id op1mr3656104pbb.86.1430833963976; Tue, 05 May 2015 06:52:43 -0700 (PDT) Received: from localhost ([180.150.157.4]) by mx.google.com with ESMTPSA id g2sm16102292pdn.3.2015.05.05.06.52.39 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 05 May 2015 06:52:40 -0700 (PDT) From: Hanjun Guo To: Marc Zyngier , Jason Cooper , Will Deacon , Catalin Marinas , "Rafael J. Wysocki" Subject: [RFC PATCH 5/9] irqchip / gic: Add stacked irqdomain support for ACPI based GICv2 init Date: Tue, 5 May 2015 21:50:53 +0800 Message-Id: <1430833857-30736-6-git-send-email-hanjun.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430833857-30736-1-git-send-email-hanjun.guo@linaro.org> References: <1430833857-30736-1-git-send-email-hanjun.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150505_065305_538203_F1439AFA X-CRM114-Status: GOOD ( 21.55 ) X-Spam-Score: -0.7 (/) Cc: Lorenzo Pieralisi , Arnd Bergmann , linux-acpi@vger.kernel.org, linaro-acpi@lists.linaro.org, linux-kernel@vger.kernel.org, Tomasz Nowicki , Olof Johansson , Hanjun Guo , Grant Likely , Thomas Gleixner , Jiang Liu , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce acpi_irq_domain for GICv2 core domain instead of referring to the irq_default_domain, based on that, pass gsi as the argument and get the gsi in gic_irq_domain_alloc() to add stacked irqdomain support for ACPI based GICv2 init. Signed-off-by: Hanjun Guo --- drivers/acpi/gsi.c | 26 +++++++++++--------------- drivers/irqchip/irq-gic.c | 32 +++++++++++++++++--------------- include/linux/irqchip/arm-gic-acpi.h | 2 ++ 3 files changed, 30 insertions(+), 30 deletions(-) diff --git a/drivers/acpi/gsi.c b/drivers/acpi/gsi.c index 38208f2..f4110d8 100644 --- a/drivers/acpi/gsi.c +++ b/drivers/acpi/gsi.c @@ -13,6 +13,7 @@ #include enum acpi_irq_model_id acpi_irq_model; +struct irq_domain *acpi_irq_domain; static unsigned int acpi_gsi_get_irq_type(int trigger, int polarity) { @@ -45,12 +46,7 @@ static unsigned int acpi_gsi_get_irq_type(int trigger, int polarity) */ int acpi_gsi_to_irq(u32 gsi, unsigned int *irq) { - /* - * Only default domain is supported at present, always find - * the mapping corresponding to default domain by passing NULL - * as irq_domain parameter - */ - *irq = irq_find_mapping(NULL, gsi); + *irq = irq_find_mapping(acpi_irq_domain, gsi); /* * *irq == 0 means no mapping, that should * be reported as a failure @@ -72,16 +68,16 @@ EXPORT_SYMBOL_GPL(acpi_gsi_to_irq); int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity) { - unsigned int irq; + int irq; unsigned int irq_type = acpi_gsi_get_irq_type(trigger, polarity); - /* - * There is no way at present to look-up the IRQ domain on ACPI, - * hence always create mapping referring to the default domain - * by passing NULL as irq_domain parameter - */ - irq = irq_create_mapping(NULL, gsi); - if (!irq) + irq = irq_find_mapping(acpi_irq_domain, gsi); + if (irq > 0) + return irq; + + irq = irq_domain_alloc_irqs(acpi_irq_domain, 1, dev_to_node(dev), + &gsi); + if (irq <= 0) return -EINVAL; /* Set irq type if specified and different than the current one */ @@ -98,7 +94,7 @@ EXPORT_SYMBOL_GPL(acpi_register_gsi); */ void acpi_unregister_gsi(u32 gsi) { - int irq = irq_find_mapping(NULL, gsi); + int irq = irq_find_mapping(acpi_irq_domain, gsi); irq_dispose_mapping(irq); } diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 476dc7b..0b712f8 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -919,15 +919,22 @@ static struct notifier_block gic_cpu_notifier = { static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *arg) { - int i, ret; + int i; irq_hw_number_t hwirq; - unsigned int type = IRQ_TYPE_NONE; - struct of_phandle_args *irq_data = arg; - ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, - irq_data->args_count, &hwirq, &type); - if (ret) - return ret; + if (domain->of_node) { /* DT case */ + int ret; + unsigned int type = IRQ_TYPE_NONE; + struct of_phandle_args *irq_data = arg; + + ret = gic_irq_domain_xlate(domain, irq_data->np, + irq_data->args, + irq_data->args_count, &hwirq, &type); + if (ret) + return ret; + } else { /* ACPI case */ + hwirq = (irq_hw_number_t)*(u32 *)arg; + } for (i = 0; i < nr_irqs; i++) gic_irq_domain_map(domain, virq + i, hwirq + i); @@ -1013,11 +1020,11 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, gic_irqs = 1020; gic->gic_irqs = gic_irqs; - if (node) { /* DT case */ + if (node || !acpi_disabled) { /* DT or ACPI case */ gic->domain = irq_domain_add_linear(node, gic_irqs, &gic_irq_domain_hierarchy_ops, gic); - } else { /* Non-DT case */ + } else { /* Non-DT and ACPI case */ /* * For primary GICs, skip over SGIs. * For secondary GICs, skip over PPIs, too. @@ -1202,13 +1209,8 @@ gic_v2_acpi_init(struct acpi_table_header *table) return -ENOMEM; } - /* - * Initialize zero GIC instance (no multi-GIC support). Also, set GIC - * as default IRQ domain to allow for GSI registration and GSI to IRQ - * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()). - */ gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL); - irq_set_default_host(gic_data[0].domain); + acpi_irq_domain = gic_data[0].domain; acpi_irq_model = ACPI_IRQ_MODEL_GIC; return 0; diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h index 021e8e8..245386d 100644 --- a/include/linux/irqchip/arm-gic-acpi.h +++ b/include/linux/irqchip/arm-gic-acpi.h @@ -21,6 +21,8 @@ #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) +extern struct irq_domain *acpi_irq_domain; + int acpi_gic_version_init(void); u8 acpi_gic_version(void); #endif /* CONFIG_ACPI */