| Message ID | 1431583811-25780-3-git-send-email-wens@csie.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, May 14, 2015 at 02:10:06PM +0800, Chen-Yu Tsai wrote: > The A80 includes an ARM CCI-400 interconnect to support multi-cluster > CPU caches. > > Also add the default clock frequency for the CPUs. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- > arch/arm/boot/dts/sun9i-a80.dtsi | 46 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 46 insertions(+) > > diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi > index ca272e92b85d..200e712fbf0e 100644 > --- a/arch/arm/boot/dts/sun9i-a80.dtsi > +++ b/arch/arm/boot/dts/sun9i-a80.dtsi > @@ -58,48 +58,64 @@ > cpu0: cpu@0 { > compatible = "arm,cortex-a7"; > device_type = "cpu"; > + cci-control-port = <&cci_control0>; > + clock-frequency = <12000000>; > reg = <0x0>; > }; > > cpu1: cpu@1 { > compatible = "arm,cortex-a7"; > device_type = "cpu"; > + cci-control-port = <&cci_control0>; > + clock-frequency = <12000000>; > reg = <0x1>; > }; > > cpu2: cpu@2 { > compatible = "arm,cortex-a7"; > device_type = "cpu"; > + cci-control-port = <&cci_control0>; > + clock-frequency = <12000000>; > reg = <0x2>; > }; > > cpu3: cpu@3 { > compatible = "arm,cortex-a7"; > device_type = "cpu"; > + cci-control-port = <&cci_control0>; > + clock-frequency = <12000000>; > reg = <0x3>; > }; > > cpu4: cpu@100 { > compatible = "arm,cortex-a15"; > device_type = "cpu"; > + cci-control-port = <&cci_control1>; > + clock-frequency = <9000000>; Isn't the clock frequency property is supposed to be the maximum frequency of that CPU in Linux? It looks odd that the A15 are clocked at a lower frequency than the A7... Maxime
On Sun, May 17, 2015 at 10:51 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > On Thu, May 14, 2015 at 02:10:06PM +0800, Chen-Yu Tsai wrote: >> The A80 includes an ARM CCI-400 interconnect to support multi-cluster >> CPU caches. >> >> Also add the default clock frequency for the CPUs. >> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> >> --- >> arch/arm/boot/dts/sun9i-a80.dtsi | 46 ++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 46 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi >> index ca272e92b85d..200e712fbf0e 100644 >> --- a/arch/arm/boot/dts/sun9i-a80.dtsi >> +++ b/arch/arm/boot/dts/sun9i-a80.dtsi >> @@ -58,48 +58,64 @@ >> cpu0: cpu@0 { >> compatible = "arm,cortex-a7"; >> device_type = "cpu"; >> + cci-control-port = <&cci_control0>; >> + clock-frequency = <12000000>; >> reg = <0x0>; >> }; >> >> cpu1: cpu@1 { >> compatible = "arm,cortex-a7"; >> device_type = "cpu"; >> + cci-control-port = <&cci_control0>; >> + clock-frequency = <12000000>; >> reg = <0x1>; >> }; >> >> cpu2: cpu@2 { >> compatible = "arm,cortex-a7"; >> device_type = "cpu"; >> + cci-control-port = <&cci_control0>; >> + clock-frequency = <12000000>; >> reg = <0x2>; >> }; >> >> cpu3: cpu@3 { >> compatible = "arm,cortex-a7"; >> device_type = "cpu"; >> + cci-control-port = <&cci_control0>; >> + clock-frequency = <12000000>; >> reg = <0x3>; >> }; >> >> cpu4: cpu@100 { >> compatible = "arm,cortex-a15"; >> device_type = "cpu"; >> + cci-control-port = <&cci_control1>; >> + clock-frequency = <9000000>; > > Isn't the clock frequency property is supposed to be the maximum > frequency of that CPU in Linux? > > It looks odd that the A15 are clocked at a lower frequency than the > A7... You're right. Looking at the FEX file, the A15s can go up to 1.8 GHz. I'll update the numbers. ChenYu
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index ca272e92b85d..200e712fbf0e 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -58,48 +58,64 @@ cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; + cci-control-port = <&cci_control0>; + clock-frequency = <12000000>; reg = <0x0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; + cci-control-port = <&cci_control0>; + clock-frequency = <12000000>; reg = <0x1>; }; cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; + cci-control-port = <&cci_control0>; + clock-frequency = <12000000>; reg = <0x2>; }; cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; + cci-control-port = <&cci_control0>; + clock-frequency = <12000000>; reg = <0x3>; }; cpu4: cpu@100 { compatible = "arm,cortex-a15"; device_type = "cpu"; + cci-control-port = <&cci_control1>; + clock-frequency = <9000000>; reg = <0x100>; }; cpu5: cpu@101 { compatible = "arm,cortex-a15"; device_type = "cpu"; + cci-control-port = <&cci_control1>; + clock-frequency = <9000000>; reg = <0x101>; }; cpu6: cpu@102 { compatible = "arm,cortex-a15"; device_type = "cpu"; + cci-control-port = <&cci_control1>; + clock-frequency = <9000000>; reg = <0x102>; }; cpu7: cpu@103 { compatible = "arm,cortex-a15"; device_type = "cpu"; + cci-control-port = <&cci_control1>; + clock-frequency = <9000000>; reg = <0x103>; }; }; @@ -522,6 +538,36 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + cci: cci@01c90000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01c90000 0x1000>; + ranges = <0x0 0x01c90000 0x10000>; + + cci_control0: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control1: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + ahb0_resets: reset@060005a0 { #reset-cells = <1>; compatible = "allwinner,sun6i-a31-clock-reset";
The A80 includes an ARM CCI-400 interconnect to support multi-cluster CPU caches. Also add the default clock frequency for the CPUs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- arch/arm/boot/dts/sun9i-a80.dtsi | 46 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)