From patchwork Mon May 18 12:59:20 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjun Guo X-Patchwork-Id: 6429261 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 34B72C0432 for ; Mon, 18 May 2015 13:15:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1BEB420411 for ; Mon, 18 May 2015 13:15:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DC97E203B7 for ; Mon, 18 May 2015 13:15:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YuKqG-0006TW-6i; Mon, 18 May 2015 13:12:24 +0000 Received: from mail-pa0-f49.google.com ([209.85.220.49]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YuKew-0004xP-W4 for linux-arm-kernel@lists.infradead.org; Mon, 18 May 2015 13:00:45 +0000 Received: by pabts4 with SMTP id ts4so151408013pab.3 for ; Mon, 18 May 2015 06:00:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5pqf0p3y0gO9coMRcxx4WJo4uOCWMrzlLVUuhS9Eav0=; b=gEVVXzxa0jQQr4le9BrY3OsSsnQLiBZ4ZAYiOoq5GRl3qSGmW0qJIlKeavhnKO9Y/z 3Yptceysh7t3J05SD1x3wIiUXOWx15HdOf0/6jozBp5MftTk1LHEy5EYmdZs1XcaHmob BZe9BIuaKsbuGN7UKFJMaFKt5pxo8zdsCOn7Y2aYmRIzPw0gRGiPEJ5kVZ8Z/xkieZKx 4fZCjQKyqz8TcahBeuzuMeOlOUpBVo9AshN8Ntb54pBm4XMYdntHpM6u03nNAZUDS00z BNxVsEUYS9KAGov4YjxAStBMx4gDpNN/U2mSjY01zG5D8yjHrXsJBPXr8jJ+P6+FCwfH pSDw== X-Gm-Message-State: ALoCoQnKo/WJmTxNE8SyOl7QdApjpzg2XQ8FuoQo90pPyoHBC+0AowNlIjWnFvBlaNOXxvWydQ4b X-Received: by 10.68.68.130 with SMTP id w2mr23931764pbt.38.1431954021598; Mon, 18 May 2015 06:00:21 -0700 (PDT) Received: from localhost ([180.150.148.224]) by mx.google.com with ESMTPSA id qe9sm10036239pbc.62.2015.05.18.06.00.20 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 18 May 2015 06:00:20 -0700 (PDT) From: Hanjun Guo To: Marc Zyngier , Jason Cooper , Will Deacon , Catalin Marinas , "Rafael J. Wysocki" Subject: [PATCH 10/11] irqchip / GICv2 / ACPI: Consolidate GICv2 ACPI related init code Date: Mon, 18 May 2015 20:59:20 +0800 Message-Id: <1431953961-22706-11-git-send-email-hanjun.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431953961-22706-1-git-send-email-hanjun.guo@linaro.org> References: <1431953961-22706-1-git-send-email-hanjun.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150518_060043_150406_D5733D86 X-CRM114-Status: GOOD ( 18.14 ) X-Spam-Score: -0.7 (/) Cc: Lorenzo Pieralisi , Arnd Bergmann , linux-acpi@vger.kernel.org, linaro-acpi@lists.linaro.org, linux-kernel@vger.kernel.org, Tomasz Nowicki , Olof Johansson , Hanjun Guo , Grant Likely , Thomas Gleixner , Jiang Liu , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Move GICv2 ACPI related init code in irq-gic.c to irq-gic-acpi.c, this can make the ACPI related GIC init code slef-contained. Introduce set_acpi_core_irqdomain() to set acpi_irqdomain then it will be no need to make gic_data[] as a global value, and it will save the confilcts with GICv3's gic_data in the later patch. acpi_gic_parse_distributor() have the same function as gic_acpi_parse_madt_distributor() to get the GIC distributor physical base address, so just remove the duplicate one, and only get the GIC version when it is unknown. Signed-off-by: Hanjun Guo --- drivers/irqchip/irq-gic-acpi.c | 95 +++++++++++++++++++++++++++++++- drivers/irqchip/irq-gic.c | 103 +---------------------------------- include/linux/irqchip/arm-gic-acpi.h | 5 ++ 3 files changed, 101 insertions(+), 102 deletions(-) diff --git a/drivers/irqchip/irq-gic-acpi.c b/drivers/irqchip/irq-gic-acpi.c index 1388d9e..8463e48 100644 --- a/drivers/irqchip/irq-gic-acpi.c +++ b/drivers/irqchip/irq-gic-acpi.c @@ -13,12 +13,16 @@ #include #include +#include #include #include +#include "irqchip.h" + /* GIC version presented in MADT GIC distributor structure */ static u8 gic_version __initdata = ACPI_MADT_GIC_VER_UNKNOWN; +/* GIC distributor physical base address, which is needed for both GICv2/3 */ static phys_addr_t dist_phy_base __initdata; u8 __init acpi_gic_version(void) @@ -26,6 +30,11 @@ u8 __init acpi_gic_version(void) return gic_version; } +void __init set_acpi_core_irqdomain(struct irq_domain *domain) +{ + acpi_irq_domain = domain; +} + static int __init acpi_gic_parse_distributor(struct acpi_subtable_header *header, const unsigned long end) @@ -37,8 +46,9 @@ acpi_gic_parse_distributor(struct acpi_subtable_header *header, if (BAD_MADT_ENTRY(dist, end)) return -EINVAL; - gic_version = dist->gic_version; dist_phy_base = dist->base_address; + if (gic_version == ACPI_MADT_GIC_VER_UNKNOWN) + gic_version = dist->gic_version; return 0; } @@ -114,3 +124,86 @@ int __init acpi_gic_version_init(void) return 0; } + +static phys_addr_t cpu_phy_base __initdata; + +static int __init +gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, + const unsigned long end) +{ + struct acpi_madt_generic_interrupt *processor; + phys_addr_t gic_cpu_base; + static int cpu_base_assigned; + + processor = (struct acpi_madt_generic_interrupt *)header; + + if (BAD_MADT_ENTRY(processor, end)) + return -EINVAL; + + /* + * There is no support for non-banked GICv1/2 register in ACPI spec. + * All CPU interface addresses have to be the same. + */ + gic_cpu_base = processor->base_address; + if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) + return -EINVAL; + + cpu_phy_base = gic_cpu_base; + cpu_base_assigned = 1; + return 0; +} + +static int __init +gic_v2_acpi_init(struct acpi_table_header *table) +{ + void __iomem *cpu_base, *dist_base; + int count; + + if (acpi_gic_version() >= ACPI_MADT_GIC_VER_V3) + return -ENODEV; + + /* Collect CPU base addresses */ + count = acpi_parse_entries(ACPI_SIG_MADT, + sizeof(struct acpi_table_madt), + gic_acpi_parse_madt_cpu, table, + ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0); + if (count <= 0) { + pr_err("No valid GICC entries exist\n"); + return -EINVAL; + } + + /* + * Find distributor base address. We expect one distributor entry since + * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade. + */ + count = acpi_parse_entries(ACPI_SIG_MADT, + sizeof(struct acpi_table_madt), + acpi_gic_parse_distributor, table, + ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0); + if (count <= 0) { + pr_err("No valid GICD entries exist\n"); + return -EINVAL; + } else if (count > 1) { + pr_err("More than one GICD entry detected\n"); + return -EINVAL; + } + + cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); + if (!cpu_base) { + pr_err("Unable to map GICC registers\n"); + return -ENOMEM; + } + + dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE); + if (!dist_base) { + pr_err("Unable to map GICD registers\n"); + iounmap(cpu_base); + return -ENOMEM; + } + + gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL); + + acpi_irq_model = ACPI_IRQ_MODEL_GIC; + return 0; +} +IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_SIG_MADT, gic_v2_acpi_init); diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 869a69f..2f934fe 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -986,6 +986,8 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, if (WARN_ON(!gic->domain)) return; + set_acpi_core_irqdomain(gic->domain); + if (gic_nr == 0) { #ifdef CONFIG_SMP set_smp_cross_call(gic_raise_softirq); @@ -1047,104 +1049,3 @@ IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); #endif - -#ifdef CONFIG_ACPI -static phys_addr_t dist_phy_base, cpu_phy_base __initdata; - -static int __init -gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, - const unsigned long end) -{ - struct acpi_madt_generic_interrupt *processor; - phys_addr_t gic_cpu_base; - static int cpu_base_assigned; - - processor = (struct acpi_madt_generic_interrupt *)header; - - if (BAD_MADT_ENTRY(processor, end)) - return -EINVAL; - - /* - * There is no support for non-banked GICv1/2 register in ACPI spec. - * All CPU interface addresses have to be the same. - */ - gic_cpu_base = processor->base_address; - if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) - return -EINVAL; - - cpu_phy_base = gic_cpu_base; - cpu_base_assigned = 1; - return 0; -} - -static int __init -gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, - const unsigned long end) -{ - struct acpi_madt_generic_distributor *dist; - - dist = (struct acpi_madt_generic_distributor *)header; - - if (BAD_MADT_ENTRY(dist, end)) - return -EINVAL; - - dist_phy_base = dist->base_address; - return 0; -} - -static int __init -gic_v2_acpi_init(struct acpi_table_header *table) -{ - void __iomem *cpu_base, *dist_base; - int count; - - if (acpi_gic_version() >= ACPI_MADT_GIC_VER_V3) - return -ENODEV; - - /* Collect CPU base addresses */ - count = acpi_parse_entries(ACPI_SIG_MADT, - sizeof(struct acpi_table_madt), - gic_acpi_parse_madt_cpu, table, - ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0); - if (count <= 0) { - pr_err("No valid GICC entries exist\n"); - return -EINVAL; - } - - /* - * Find distributor base address. We expect one distributor entry since - * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade. - */ - count = acpi_parse_entries(ACPI_SIG_MADT, - sizeof(struct acpi_table_madt), - gic_acpi_parse_madt_distributor, table, - ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0); - if (count <= 0) { - pr_err("No valid GICD entries exist\n"); - return -EINVAL; - } else if (count > 1) { - pr_err("More than one GICD entry detected\n"); - return -EINVAL; - } - - cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); - if (!cpu_base) { - pr_err("Unable to map GICC registers\n"); - return -ENOMEM; - } - - dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE); - if (!dist_base) { - pr_err("Unable to map GICD registers\n"); - iounmap(cpu_base); - return -ENOMEM; - } - - gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL); - acpi_irq_domain = gic_data[0].domain; - - acpi_irq_model = ACPI_IRQ_MODEL_GIC; - return 0; -} -IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_SIG_MADT, gic_v2_acpi_init); -#endif diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h index 245386d..f4a17c7 100644 --- a/include/linux/irqchip/arm-gic-acpi.h +++ b/include/linux/irqchip/arm-gic-acpi.h @@ -25,5 +25,10 @@ extern struct irq_domain *acpi_irq_domain; int acpi_gic_version_init(void); u8 acpi_gic_version(void); + +void set_acpi_core_irqdomain(struct irq_domain *domain); +#else +#define set_acpi_core_irqdomain(domain) #endif /* CONFIG_ACPI */ + #endif /* ARM_GIC_ACPI_H_ */