From patchwork Mon May 18 22:11:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 6432441 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D7831C0432 for ; Mon, 18 May 2015 22:14:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8DBEC2043C for ; Mon, 18 May 2015 22:14:49 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5E6E020430 for ; Mon, 18 May 2015 22:14:48 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YuTH5-00031n-NB; Mon, 18 May 2015 22:12:39 +0000 Received: from mail-wg0-x22f.google.com ([2a00:1450:400c:c00::22f]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YuTGm-0002yL-5K for linux-arm-kernel@lists.infradead.org; Mon, 18 May 2015 22:12:21 +0000 Received: by wgfl8 with SMTP id l8so52019752wgf.2 for ; Mon, 18 May 2015 15:11:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jjRcX9QnHc3lQCYaSu2Jr5dNni8upTo6UbAyK+23VYg=; b=VP7mXXIjWA72tvMAPUO5SoRm/9PATHWYeFq+AY+7VbujeiFuSXQzOarLLmr19KBaHK 3F4bQ190ToHNVAr6k+vJF1OUbP2MXrBSMoahD29sHQ8N4TzYZ4AHCrusZA4j5M07fI2g Gi1wNdaVYENDVL85/a9FlS8xMIltZAIFRafOVoBDKD6T48+ZeA75yWPhjEtXVogagpEr /UtexQ/ZthWT01zSXKNRH0H6VaN+U28+lhCxTQEl38IPN8qeSV0Zhf+92HfoEi2C0H7O JBp7K7b/E60htrV8QWLzKmfvPhKQx0smMDCcu5vOtqRSA6cQyY4EziY22RUGDn6DuctZ FmnQ== X-Received: by 10.194.60.106 with SMTP id g10mr32677872wjr.121.1431987116683; Mon, 18 May 2015 15:11:56 -0700 (PDT) Received: from fangorn.rup.mentorg.com (nat-min.mentorg.com. [139.181.32.34]) by mx.google.com with ESMTPSA id b10sm14395287wic.1.2015.05.18.15.11.55 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 May 2015 15:11:55 -0700 (PDT) From: Dmitry Eremin-Solenikov To: Russell King , Thomas Gleixner , Jason Cooper Subject: [PATCH 2/2] ARM: sa1100: move irq driver to drivers/irqchip/ Date: Tue, 19 May 2015 01:11:36 +0300 Message-Id: <1431987096-16308-3-git-send-email-dbaryshkov@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1431987096-16308-1-git-send-email-dbaryshkov@gmail.com> References: <1431987096-16308-1-git-send-email-dbaryshkov@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150518_151220_542629_2CA16BBA X-CRM114-Status: GOOD ( 20.97 ) X-Spam-Score: -0.8 (/) Cc: linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Move current sa11x0 IRQ driver to the irqchip subsystem. Signed-off-by: Dmitry Eremin-Solenikov --- arch/arm/mach-sa1100/Makefile | 2 +- arch/arm/mach-sa1100/irq.c | 177 ------------------------------------------ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sa11x0.c | 175 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 177 insertions(+), 178 deletions(-) delete mode 100644 arch/arm/mach-sa1100/irq.c create mode 100644 drivers/irqchip/irq-sa11x0.c diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile index 61ff91e..ebc4d58 100644 --- a/arch/arm/mach-sa1100/Makefile +++ b/arch/arm/mach-sa1100/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := clock.o generic.o irq.o #nmi-oopser.o +obj-y := clock.o generic.o #nmi-oopser.o # Specific board support obj-$(CONFIG_SA1100_ASSABET) += assabet.o diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c deleted file mode 100644 index fdec5ed..0000000 --- a/arch/arm/mach-sa1100/irq.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * linux/arch/arm/mach-sa1100/irq.c - * - * Copyright (C) 2015 Dmitry Eremin-Solenikov - * Copyright (C) 1999-2001 Nicolas Pitre - * - * Generic IRQ handling for the SA11x0. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -#define ICIP 0x00 /* IC IRQ Pending reg. */ -#define ICMR 0x04 /* IC Mask Reg. */ -#define ICLR 0x08 /* IC Level Reg. */ -#define ICCR 0x0C /* IC Control Reg. */ -#define ICFP 0x10 /* IC FIQ Pending reg. */ -#define ICPR 0x20 /* IC Pending Reg. */ - -static void __iomem *iobase; - -/* - * We don't need to ACK IRQs on the SA1100 unless they're GPIOs - * this is for internal IRQs i.e. from IRQ LCD to RTCAlrm. - */ -static void sa1100_mask_irq(struct irq_data *d) -{ - u32 reg; - - reg = readl_relaxed(iobase + ICMR); - reg &= ~BIT(d->hwirq); - writel_relaxed(reg, iobase + ICMR); -} - -static void sa1100_unmask_irq(struct irq_data *d) -{ - u32 reg; - - reg = readl_relaxed(iobase + ICMR); - reg |= BIT(d->hwirq); - writel_relaxed(reg, iobase + ICMR); -} - -static int sa1100_set_wake(struct irq_data *d, unsigned int on) -{ - return sa11x0_sc_set_wake(d->hwirq, on); -} - -static struct irq_chip sa1100_normal_chip = { - .name = "SC", - .irq_ack = sa1100_mask_irq, - .irq_mask = sa1100_mask_irq, - .irq_unmask = sa1100_unmask_irq, - .irq_set_wake = sa1100_set_wake, -}; - -static int sa1100_normal_irqdomain_map(struct irq_domain *d, - unsigned int irq, irq_hw_number_t hwirq) -{ - irq_set_chip_and_handler(irq, &sa1100_normal_chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - - return 0; -} - -static struct irq_domain_ops sa1100_normal_irqdomain_ops = { - .map = sa1100_normal_irqdomain_map, - .xlate = irq_domain_xlate_onetwocell, -}; - -static struct irq_domain *sa1100_normal_irqdomain; - -static struct sa1100irq_state { - unsigned int saved; - unsigned int icmr; - unsigned int iclr; - unsigned int iccr; -} sa1100irq_state; - -static int sa1100irq_suspend(void) -{ - struct sa1100irq_state *st = &sa1100irq_state; - - st->saved = 1; - st->icmr = readl_relaxed(iobase + ICMR); - st->iclr = readl_relaxed(iobase + ICLR); - st->iccr = readl_relaxed(iobase + ICCR); - - /* - * Disable all GPIO-based interrupts. - */ - writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR); - - return 0; -} - -static void sa1100irq_resume(void) -{ - struct sa1100irq_state *st = &sa1100irq_state; - - if (st->saved) { - writel_relaxed(st->iccr, iobase + ICCR); - writel_relaxed(st->iclr, iobase + ICLR); - - writel_relaxed(st->icmr, iobase + ICMR); - } -} - -static struct syscore_ops sa1100irq_syscore_ops = { - .suspend = sa1100irq_suspend, - .resume = sa1100irq_resume, -}; - -static int __init sa1100irq_init_devicefs(void) -{ - register_syscore_ops(&sa1100irq_syscore_ops); - return 0; -} - -device_initcall(sa1100irq_init_devicefs); - -static asmlinkage void __exception_irq_entry -sa1100_handle_irq(struct pt_regs *regs) -{ - uint32_t icip, icmr, mask; - - do { - icip = readl_relaxed(iobase + ICIP); - icmr = readl_relaxed(iobase + ICMR); - mask = icip & icmr; - - if (mask == 0) - break; - - handle_domain_irq(sa1100_normal_irqdomain, - ffs(mask) - 1, regs); - } while (1); -} - -void __init sa11x0_init_irq_nodt(int irq_start, resource_size_t io_start) -{ - iobase = ioremap(io_start, SZ_64K); - if (WARN_ON(!iobase)) - return; - - /* disable all IRQs */ - writel_relaxed(0, iobase + ICMR); - - /* all IRQs are IRQ, not FIQ */ - writel_relaxed(0, iobase + ICLR); - - /* - * Whatever the doc says, this has to be set for the wait-on-irq - * instruction to work... on a SA1100 rev 9 at least. - */ - writel_relaxed(1, iobase + ICCR); - - sa1100_normal_irqdomain = irq_domain_add_simple(NULL, - 32, irq_start, - &sa1100_normal_irqdomain_ops, NULL); - - set_handle_irq(sa1100_handle_irq); -} diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index dda4927..49f372a 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -47,3 +47,4 @@ obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o obj-$(CONFIG_ARCH_MEDIATEK) += irq-mtk-sysirq.o obj-$(CONFIG_ARCH_DIGICOLOR) += irq-digicolor.o +obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o diff --git a/drivers/irqchip/irq-sa11x0.c b/drivers/irqchip/irq-sa11x0.c new file mode 100644 index 0000000..97d257b --- /dev/null +++ b/drivers/irqchip/irq-sa11x0.c @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2015 Dmitry Eremin-Solenikov + * Copyright (C) 1999-2001 Nicolas Pitre + * + * Generic IRQ handling for the SA11x0. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#define ICIP 0x00 /* IC IRQ Pending reg. */ +#define ICMR 0x04 /* IC Mask Reg. */ +#define ICLR 0x08 /* IC Level Reg. */ +#define ICCR 0x0C /* IC Control Reg. */ +#define ICFP 0x10 /* IC FIQ Pending reg. */ +#define ICPR 0x20 /* IC Pending Reg. */ + +static void __iomem *iobase; + +/* + * We don't need to ACK IRQs on the SA1100 unless they're GPIOs + * this is for internal IRQs i.e. from IRQ LCD to RTCAlrm. + */ +static void sa1100_mask_irq(struct irq_data *d) +{ + u32 reg; + + reg = readl_relaxed(iobase + ICMR); + reg &= ~BIT(d->hwirq); + writel_relaxed(reg, iobase + ICMR); +} + +static void sa1100_unmask_irq(struct irq_data *d) +{ + u32 reg; + + reg = readl_relaxed(iobase + ICMR); + reg |= BIT(d->hwirq); + writel_relaxed(reg, iobase + ICMR); +} + +static int sa1100_set_wake(struct irq_data *d, unsigned int on) +{ + return sa11x0_sc_set_wake(d->hwirq, on); +} + +static struct irq_chip sa1100_normal_chip = { + .name = "SC", + .irq_ack = sa1100_mask_irq, + .irq_mask = sa1100_mask_irq, + .irq_unmask = sa1100_unmask_irq, + .irq_set_wake = sa1100_set_wake, +}; + +static int sa1100_normal_irqdomain_map(struct irq_domain *d, + unsigned int irq, irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &sa1100_normal_chip, + handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + + return 0; +} + +static struct irq_domain_ops sa1100_normal_irqdomain_ops = { + .map = sa1100_normal_irqdomain_map, + .xlate = irq_domain_xlate_onetwocell, +}; + +static struct irq_domain *sa1100_normal_irqdomain; + +static struct sa1100irq_state { + unsigned int saved; + unsigned int icmr; + unsigned int iclr; + unsigned int iccr; +} sa1100irq_state; + +static int sa1100irq_suspend(void) +{ + struct sa1100irq_state *st = &sa1100irq_state; + + st->saved = 1; + st->icmr = readl_relaxed(iobase + ICMR); + st->iclr = readl_relaxed(iobase + ICLR); + st->iccr = readl_relaxed(iobase + ICCR); + + /* + * Disable all GPIO-based interrupts. + */ + writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR); + + return 0; +} + +static void sa1100irq_resume(void) +{ + struct sa1100irq_state *st = &sa1100irq_state; + + if (st->saved) { + writel_relaxed(st->iccr, iobase + ICCR); + writel_relaxed(st->iclr, iobase + ICLR); + + writel_relaxed(st->icmr, iobase + ICMR); + } +} + +static struct syscore_ops sa1100irq_syscore_ops = { + .suspend = sa1100irq_suspend, + .resume = sa1100irq_resume, +}; + +static int __init sa1100irq_init_devicefs(void) +{ + register_syscore_ops(&sa1100irq_syscore_ops); + return 0; +} + +device_initcall(sa1100irq_init_devicefs); + +static asmlinkage void __exception_irq_entry +sa1100_handle_irq(struct pt_regs *regs) +{ + uint32_t icip, icmr, mask; + + do { + icip = readl_relaxed(iobase + ICIP); + icmr = readl_relaxed(iobase + ICMR); + mask = icip & icmr; + + if (mask == 0) + break; + + handle_domain_irq(sa1100_normal_irqdomain, + ffs(mask) - 1, regs); + } while (1); +} + +void __init sa11x0_init_irq_nodt(int irq_start, resource_size_t io_start) +{ + iobase = ioremap(io_start, SZ_64K); + if (WARN_ON(!iobase)) + return; + + /* disable all IRQs */ + writel_relaxed(0, iobase + ICMR); + + /* all IRQs are IRQ, not FIQ */ + writel_relaxed(0, iobase + ICLR); + + /* + * Whatever the doc says, this has to be set for the wait-on-irq + * instruction to work... on a SA1100 rev 9 at least. + */ + writel_relaxed(1, iobase + ICCR); + + sa1100_normal_irqdomain = irq_domain_add_simple(NULL, + 32, irq_start, + &sa1100_normal_irqdomain_ops, NULL); + + set_handle_irq(sa1100_handle_irq); +}