From patchwork Fri May 22 15:29:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 6465571 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 421999F1C1 for ; Fri, 22 May 2015 15:35:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 562C0202FE for ; Fri, 22 May 2015 15:35:44 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4FD6E200E8 for ; Fri, 22 May 2015 15:35:43 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YvowP-00071G-VN; Fri, 22 May 2015 15:32:54 +0000 Received: from mail-pa0-f48.google.com ([209.85.220.48]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YvovG-00064t-Fa for linux-arm-kernel@lists.infradead.org; Fri, 22 May 2015 15:31:43 +0000 Received: by pabru16 with SMTP id ru16so22417198pab.1 for ; Fri, 22 May 2015 08:31:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gjzDAYmwOqptCwThhlz+PKCg8IkyXP+aFy0nkmCtKek=; b=RKu514oZ+teuv3hPbyWQnr1kH4RQxCVjgeOrPFAkdICkBlwRRiqW8PKQ0F9z2Nm08A Tk2U0VaqItka9PeYi5c00NdJCtvVIXKSLtoBQvAGKH19pKCkPWOI2diJNgUZo30nymiI pvpF5/ojbHlw3s5+pzUah0DfrLbO7pOwMsXfG8fVsJYlajKeK0Q9dcr06hGjHSgouJWF ojYSErlwbSs/JGzmH7grRAocFjNS0yTt54YfynaFM23E511YOpl/GDpTW/BKkYGd1NKg Lio0VSV4INO4RxVm7/UHAji/is4JCawYTItPE7GxHmxgjsHW9x2QAJo8tIze/y0DQF3C CA+Q== X-Gm-Message-State: ALoCoQnC9iUVsBT2KUJq2vwm/d0G1vZhN7zsFncfA08QVKYroq+SUFZoOwNg4orAK6pCWVPEYwVd X-Received: by 10.68.113.194 with SMTP id ja2mr16317622pbb.163.1432308680860; Fri, 22 May 2015 08:31:20 -0700 (PDT) Received: from localhost.localdomain ([107.6.117.178]) by mx.google.com with ESMTPSA id as1sm2474485pbc.39.2015.05.22.08.31.15 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 22 May 2015 08:31:20 -0700 (PDT) From: Shawn Guo To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 01/12] ARM: imx: use relaxed IO accessor in timer driver Date: Fri, 22 May 2015 23:29:48 +0800 Message-Id: <1432308599-28643-2-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432308599-28643-1-git-send-email-shawn.guo@linaro.org> References: <1432308599-28643-1-git-send-email-shawn.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150522_083142_646895_BFCFEF3F X-CRM114-Status: GOOD ( 16.16 ) X-Spam-Score: -1.8 (-) Cc: Shawn Guo , Daniel Lezcano , Arnd Bergmann , kernel@pengutronix.de, Shenwei Wang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Replace the __raw_readl/__raw_writel with readl_relaxed/writel_relaxed which is endian-safe, as a step of moving the driver code into folder drivers/clocksource. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/time.c | 48 ++++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index ab5ee1c445f3..376d5d8ccfb8 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -91,19 +91,19 @@ static inline void gpt_irq_disable(void) unsigned int tmp; if (timer_is_v2()) - __raw_writel(0, timer_base + V2_IR); + writel_relaxed(0, timer_base + V2_IR); else { - tmp = __raw_readl(timer_base + MXC_TCTL); - __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); + tmp = readl_relaxed(timer_base + MXC_TCTL); + writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); } } static inline void gpt_irq_enable(void) { if (timer_is_v2()) - __raw_writel(1<<0, timer_base + V2_IR); + writel_relaxed(1<<0, timer_base + V2_IR); else { - __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, + writel_relaxed(readl_relaxed(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); } } @@ -112,26 +112,26 @@ static void gpt_irq_acknowledge(void) { if (timer_is_v1()) { if (cpu_is_mx1()) - __raw_writel(0, timer_base + MX1_2_TSTAT); + writel_relaxed(0, timer_base + MX1_2_TSTAT); else - __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, + writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT); } else if (timer_is_v2()) - __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); + writel_relaxed(V2_TSTAT_OF1, timer_base + V2_TSTAT); } static void __iomem *sched_clock_reg; static u64 notrace mxc_read_sched_clock(void) { - return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; + return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0; } static struct delay_timer imx_delay_timer; static unsigned long imx_read_current_timer(void) { - return __raw_readl(sched_clock_reg); + return readl_relaxed(sched_clock_reg); } static int __init mxc_clocksource_init(struct clk *timer_clk) @@ -157,11 +157,11 @@ static int mx1_2_set_next_event(unsigned long evt, { unsigned long tcmp; - tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt; + tcmp = readl_relaxed(timer_base + MX1_2_TCN) + evt; - __raw_writel(tcmp, timer_base + MX1_2_TCMP); + writel_relaxed(tcmp, timer_base + MX1_2_TCMP); - return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ? + return (int)(tcmp - readl_relaxed(timer_base + MX1_2_TCN)) < 0 ? -ETIME : 0; } @@ -170,12 +170,12 @@ static int v2_set_next_event(unsigned long evt, { unsigned long tcmp; - tcmp = __raw_readl(timer_base + V2_TCN) + evt; + tcmp = readl_relaxed(timer_base + V2_TCN) + evt; - __raw_writel(tcmp, timer_base + V2_TCMP); + writel_relaxed(tcmp, timer_base + V2_TCMP); return evt < 0x7fffffff && - (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ? + (int)(tcmp - readl_relaxed(timer_base + V2_TCN)) < 0 ? -ETIME : 0; } @@ -206,10 +206,10 @@ static void mxc_set_mode(enum clock_event_mode mode, if (mode != clockevent_mode) { /* Set event time into far-far future */ if (timer_is_v2()) - __raw_writel(__raw_readl(timer_base + V2_TCN) - 3, + writel_relaxed(readl_relaxed(timer_base + V2_TCN) - 3, timer_base + V2_TCMP); else - __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3, + writel_relaxed(readl_relaxed(timer_base + MX1_2_TCN) - 3, timer_base + MX1_2_TCMP); /* Clear pending interrupt */ @@ -259,9 +259,9 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) uint32_t tstat; if (timer_is_v2()) - tstat = __raw_readl(timer_base + V2_TSTAT); + tstat = readl_relaxed(timer_base + V2_TSTAT); else - tstat = __raw_readl(timer_base + MX1_2_TSTAT); + tstat = readl_relaxed(timer_base + MX1_2_TSTAT); gpt_irq_acknowledge(); @@ -316,8 +316,8 @@ static void __init _mxc_timer_init(int irq, * Initialise to a known state (all timers off, and timing reset) */ - __raw_writel(0, timer_base + MXC_TCTL); - __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ + writel_relaxed(0, timer_base + MXC_TCTL); + writel_relaxed(0, timer_base + MXC_TPRER); /* see datasheet note */ if (timer_is_v2()) { tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; @@ -325,7 +325,7 @@ static void __init _mxc_timer_init(int irq, tctl_val |= V2_TCTL_CLK_OSC_DIV8; if (cpu_is_imx6dl() || cpu_is_imx6sx()) { /* 24 / 8 = 3 MHz */ - __raw_writel(7 << V2_TPRER_PRE24M, + writel_relaxed(7 << V2_TPRER_PRE24M, timer_base + MXC_TPRER); tctl_val |= V2_TCTL_24MEN; } @@ -336,7 +336,7 @@ static void __init _mxc_timer_init(int irq, tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; } - __raw_writel(tctl_val, timer_base + MXC_TCTL); + writel_relaxed(tctl_val, timer_base + MXC_TCTL); /* init and register the timer to the framework */ mxc_clocksource_init(clk_per);