From patchwork Fri May 22 15:29:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 6465601 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 23C3FC0020 for ; Fri, 22 May 2015 15:38:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E30FF200F3 for ; Fri, 22 May 2015 15:38:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1C0C2200E8 for ; Fri, 22 May 2015 15:38:47 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YvoyM-0008J7-Gs; Fri, 22 May 2015 15:34:54 +0000 Received: from merlin.infradead.org ([2001:4978:20e::2]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YvovX-0006UC-Tw for linux-arm-kernel@bombadil.infradead.org; Fri, 22 May 2015 15:32:00 +0000 Received: from mail-pa0-f41.google.com ([209.85.220.41]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YvovU-0003NG-CJ for linux-arm-kernel@lists.infradead.org; Fri, 22 May 2015 15:31:57 +0000 Received: by pacwv17 with SMTP id wv17so22351527pac.2 for ; Fri, 22 May 2015 08:31:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Tn/pyynUJSEPOIzdOUlWAeeCyo/d1Lh5OW030NnqvL8=; b=HpLqeKLR0Uk7VTSfUl+oz8QAoGx3B8R66vv+9hFsCHFeJcnpmY9hzCe6a+42IkdaM7 +xZnb27ndh2KFhCdJkqWsMjUpjyLOHs6dzUkoUwLWDMaHoIh5L4iENFsa7Gv7wJBvG66 uKjKGlAyYTEydEsw3LnzjqN+tyu0/h32H8ljputQyexlJgpHwEig8S+/BtOsax7tSVBl xmUqQocO/mx6wIXfWsLAubdy4jgTqqBUY66XHVc6qRQEYibOQVgkoFhXdjYSw5xMTqPw WpELK8Lfh2FbC3+vHDh6sy8GPXbKePhHCzsW39/4RuDBIUaT3uiSzbNyqqHKbItyneWD j5ZA== X-Gm-Message-State: ALoCoQkbgQL2+ocl1RErcds3hGO69J6YKYEuVHca2W0rn3r8GaoV94qqFcrZsQAW6AtlWIgmiQpr X-Received: by 10.70.46.161 with SMTP id w1mr16967366pdm.16.1432308690626; Fri, 22 May 2015 08:31:30 -0700 (PDT) Received: from localhost.localdomain ([107.6.117.178]) by mx.google.com with ESMTPSA id as1sm2474485pbc.39.2015.05.22.08.31.26 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 22 May 2015 08:31:29 -0700 (PDT) From: Shawn Guo To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 03/12] ARM: imx: define an enum for gpt timer device type Date: Fri, 22 May 2015 23:29:50 +0800 Message-Id: <1432308599-28643-4-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432308599-28643-1-git-send-email-shawn.guo@linaro.org> References: <1432308599-28643-1-git-send-email-shawn.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150522_113156_574327_A2A880C1 X-CRM114-Status: GOOD ( 17.75 ) X-Spam-Score: -2.6 (--) Cc: Shawn Guo , Daniel Lezcano , Arnd Bergmann , kernel@pengutronix.de, Shenwei Wang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Define an enum for gpt timer device type in include/soc/imx/timer.h to tell the gpt block differences among SoCs. Update non-DT users (clock drivers) to pass the device type. As we now have include/soc/imx/timer.h, the declaration of mxc_timer_init() is moved into there as the best fit. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/time.c | 6 +++++- drivers/clk/imx/clk-imx1.c | 3 ++- drivers/clk/imx/clk-imx21.c | 3 ++- drivers/clk/imx/clk-imx27.c | 3 ++- drivers/clk/imx/clk-imx31.c | 3 ++- drivers/clk/imx/clk-imx35.c | 3 ++- drivers/clk/imx/clk.h | 7 ------- include/soc/imx/timer.h | 26 ++++++++++++++++++++++++++ 8 files changed, 41 insertions(+), 13 deletions(-) create mode 100644 include/soc/imx/timer.h diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index 7c131e1b2637..307cbc7abc8e 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -32,6 +32,7 @@ #include #include #include +#include #include @@ -86,6 +87,7 @@ static struct clock_event_device clockevent_mxc; static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; struct imx_timer { + enum imx_gpt_type type; void __iomem *base; int irq; struct clk *clk_per; @@ -356,7 +358,7 @@ static void __init _mxc_timer_init(struct imx_timer *imxtm) setup_irq(imxtm->irq, &mxc_timer_irq); } -void __init mxc_timer_init(unsigned long pbase, int irq) +void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type) { struct imx_timer *imxtm; @@ -369,6 +371,8 @@ void __init mxc_timer_init(unsigned long pbase, int irq) imxtm->base = ioremap(pbase, SZ_4K); BUG_ON(!imxtm->base); + imxtm->type = type; + _mxc_timer_init(imxtm); } diff --git a/drivers/clk/imx/clk-imx1.c b/drivers/clk/imx/clk-imx1.c index c9812dbacac2..c2647fa19f28 100644 --- a/drivers/clk/imx/clk-imx1.c +++ b/drivers/clk/imx/clk-imx1.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include "clk.h" @@ -102,7 +103,7 @@ int __init mx1_clocks_init(unsigned long fref) clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0"); clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0"); - mxc_timer_init(MX1_TIM1_BASE_ADDR, MX1_TIM1_INT); + mxc_timer_init(MX1_TIM1_BASE_ADDR, MX1_TIM1_INT, GPT_TYPE_IMX1); return 0; } diff --git a/drivers/clk/imx/clk-imx21.c b/drivers/clk/imx/clk-imx21.c index 0ca842cf4ca7..dba987e3b89f 100644 --- a/drivers/clk/imx/clk-imx21.c +++ b/drivers/clk/imx/clk-imx21.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include "clk.h" @@ -156,7 +157,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href) clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0"); clk_register_clkdev(clk[IMX21_CLK_OWIRE_GATE], NULL, "mxc_w1.0"); - mxc_timer_init(MX21_GPT1_BASE_ADDR, MX21_INT_GPT1); + mxc_timer_init(MX21_GPT1_BASE_ADDR, MX21_INT_GPT1, GPT_TYPE_IMX21); return 0; } diff --git a/drivers/clk/imx/clk-imx27.c b/drivers/clk/imx/clk-imx27.c index df2dfc081c71..d9d50d54ef2a 100644 --- a/drivers/clk/imx/clk-imx27.c +++ b/drivers/clk/imx/clk-imx27.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include "clk.h" @@ -233,7 +234,7 @@ int __init mx27_clocks_init(unsigned long fref) clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0"); clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0"); - mxc_timer_init(MX27_GPT1_BASE_ADDR, MX27_INT_GPT1); + mxc_timer_init(MX27_GPT1_BASE_ADDR, MX27_INT_GPT1, GPT_TYPE_IMX21); return 0; } diff --git a/drivers/clk/imx/clk-imx31.c b/drivers/clk/imx/clk-imx31.c index a55290c1c264..fe66c40b7be2 100644 --- a/drivers/clk/imx/clk-imx31.c +++ b/drivers/clk/imx/clk-imx31.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include "clk.h" @@ -198,7 +199,7 @@ int __init mx31_clocks_init(unsigned long fref) mx31_revision(); clk_disable_unprepare(clk[iim_gate]); - mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT); + mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31); return 0; } diff --git a/drivers/clk/imx/clk-imx35.c b/drivers/clk/imx/clk-imx35.c index f2f3b8164f7b..69138ba3dec7 100644 --- a/drivers/clk/imx/clk-imx35.c +++ b/drivers/clk/imx/clk-imx35.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include "clk.h" @@ -293,7 +294,7 @@ int __init mx35_clocks_init(void) imx_print_silicon_rev("i.MX35", mx35_revision()); - mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT); + mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT, GPT_TYPE_IMX31); return 0; } diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 8b112182a83b..1049b0c7d818 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -6,13 +6,6 @@ extern spinlock_t imx_ccm_lock; -/* - * This is a stop-gap solution for clock drivers like imx1/imx21 which call - * mxc_timer_init() to initialize timer for non-DT boot. It can be removed - * when these legacy non-DT support is converted or dropped. - */ -void mxc_timer_init(unsigned long pbase, int irq); - void imx_check_clocks(struct clk *clks[], unsigned int count); extern void imx_cscmr1_fixup(u32 *val); diff --git a/include/soc/imx/timer.h b/include/soc/imx/timer.h new file mode 100644 index 000000000000..bbbafd65f464 --- /dev/null +++ b/include/soc/imx/timer.h @@ -0,0 +1,26 @@ +/* + * Copyright 2015 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __SOC_IMX_TIMER_H__ +#define __SOC_IMX_TIMER_H__ + +enum imx_gpt_type { + GPT_TYPE_IMX1, /* i.MX1 */ + GPT_TYPE_IMX21, /* i.MX21/27 */ + GPT_TYPE_IMX31, /* i.MX31/35/25/37/51/6Q */ + GPT_TYPE_IMX6DL, /* i.MX6DL/SX/SL */ +}; + +/* + * This is a stop-gap solution for clock drivers like imx1/imx21 which call + * mxc_timer_init() to initialize timer for non-DT boot. It can be removed + * when these legacy non-DT support is converted or dropped. + */ +void mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type); + +#endif /* __SOC_IMX_TIMER_H__ */