From patchwork Fri May 22 20:41:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 6467731 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C09F09F1CC for ; Fri, 22 May 2015 20:45:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C2A162050B for ; Fri, 22 May 2015 20:45:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C02E02047B for ; Fri, 22 May 2015 20:45:13 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yvtm6-0008D3-IG; Fri, 22 May 2015 20:42:34 +0000 Received: from mail-wg0-f46.google.com ([74.125.82.46]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YvtlZ-00082X-8A for linux-arm-kernel@lists.infradead.org; Fri, 22 May 2015 20:42:02 +0000 Received: by wgbgq6 with SMTP id gq6so27833277wgb.3 for ; Fri, 22 May 2015 13:41:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ptJLFTmrm8sszbrF9t7PxAPV4dsKti1Z30z+eC2No1Y=; b=Ru5P5fmJidQCrdrvnVEfy0svh29oqxfj6VDNqR/ULhgN0QBD/yrpI64IiD7t/knqf/ xOLQC9BqGLzTzRInyNwKKzmqogf3KjSBGQwDhS/hHJyh9KLY7vmosV9HtmfcYzZm7ZY9 fwNehooOMABbxJS0Bq2wVw4s9KrfXwqyBdPSNNAa5SgOps2yp+gqDxWLJLyReQkRNYYB 8YYsaaISlL9WvzGGNp/UWXBhRD6WbTjuXDPvSjoiZc/OFTJfAlNX5DGhoK6jcq/XXyX6 iGn64haD1tJ+ztThwPeUl/xFbPVi8KwbFcUl8qX95aacAhbwpFL8j+OK7ahKxXwXoqlc GFPA== X-Gm-Message-State: ALoCoQkQRvbwzffBsIJ4gmofcdcdnkGzeR/vcHeTr+CqPaFPNnWEFr9J3T5Rtwr/jFNGltv8RI4Q X-Received: by 10.180.97.164 with SMTP id eb4mr11052628wib.3.1432327299601; Fri, 22 May 2015 13:41:39 -0700 (PDT) Received: from scallop.lan (cpc4-aztw19-0-0-cust71.18-1.cable.virginm.net. [82.33.25.72]) by mx.google.com with ESMTPSA id g11sm4759204wjr.25.2015.05.22.13.41.37 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 22 May 2015 13:41:38 -0700 (PDT) From: Daniel Thompson To: Mike Turquette , Stephen Boyd Subject: [RFC PATCH 3/3] ARM: dts: stm32f429: Adopt STM32F4 clock driver Date: Fri, 22 May 2015 21:41:13 +0100 Message-Id: <1432327273-6810-4-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1432327273-6810-1-git-send-email-daniel.thompson@linaro.org> References: <1432327273-6810-1-git-send-email-daniel.thompson@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150522_134201_648199_7953E1A2 X-CRM114-Status: GOOD ( 10.93 ) X-Spam-Score: -0.7 (/) Cc: Mark Rutland , devicetree@vger.kernel.org, Daniel Thompson , linaro-kernel@lists.linaro.org, Russell King , Pawel Moll , Ian Campbell , patches@linaro.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Kamil Lulko , Rob Herring , Maxime Coquelin , Kumar Gala , Andreas Farber , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP New bindings and driver have been created for STM32F42xxx series parts. This patch integrates these changes. Note: Earlier device tree blobs (those without st,stm32f42xxx compatibles for the rcc) could still be used to boot basic systems. Such systems rely on the bootloader to configure the clocks for vital periperhals. Signed-off-by: Daniel Thompson --- arch/arm/boot/dts/stm32f429.dtsi | 83 +++++++++++++--------------------------- 1 file changed, 26 insertions(+), 57 deletions(-) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index aa3b3e3..6da8d7f 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -50,48 +50,10 @@ / { clocks { - clk_sysclk: clk-sysclk { + clk_hse: clk-hse { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <168000000>; - }; - - clk_hclk: clk-hclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <168000000>; - }; - - clk_pclk1: clk-pclk1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <42000000>; - }; - - clk_pclk2: clk-pclk2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <84000000>; - }; - - clk_pmtr1: clk-pmtr1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <84000000>; - }; - - clk_pmtr2: clk-pmtr2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <168000000>; - }; - - clk_systick: clk-systick { - compatible = "fixed-factor-clock"; - clocks = <&clk_hclk>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; + clock-frequency = <8000000>; }; }; @@ -101,7 +63,7 @@ reg = <0x40000000 0x400>; interrupts = <28>; resets = <&rcc STM32F4_APB1_RESET(TIM2)>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 128>; status = "disabled"; }; @@ -110,7 +72,7 @@ reg = <0x40000400 0x400>; interrupts = <29>; resets = <&rcc STM32F4_APB1_RESET(TIM3)>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 129>; status = "disabled"; }; @@ -119,7 +81,7 @@ reg = <0x40000800 0x400>; interrupts = <30>; resets = <&rcc STM32F4_APB1_RESET(TIM4)>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 130>; status = "disabled"; }; @@ -128,7 +90,7 @@ reg = <0x40000c00 0x400>; interrupts = <50>; resets = <&rcc STM32F4_APB1_RESET(TIM5)>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 131>; status = "disabled"; }; @@ -137,7 +99,7 @@ reg = <0x40001000 0x400>; interrupts = <54>; resets = <&rcc STM32F4_APB1_RESET(TIM6)>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 132>; status = "disabled"; }; @@ -146,7 +108,7 @@ reg = <0x40001400 0x400>; interrupts = <55>; resets = <&rcc STM32F4_APB1_RESET(TIM7)>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 133>; status = "disabled"; }; @@ -154,7 +116,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; interrupts = <38>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 145>; status = "disabled"; }; @@ -162,7 +124,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; interrupts = <39>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 146>; status = "disabled"; }; @@ -170,7 +132,7 @@ compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; interrupts = <52>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 147>; status = "disabled"; }; @@ -178,7 +140,7 @@ compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; interrupts = <53>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 148>; status = "disabled"; }; @@ -186,7 +148,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40007800 0x400>; interrupts = <82>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 158>; status = "disabled"; }; @@ -194,7 +156,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40007c00 0x400>; interrupts = <83>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 159>; status = "disabled"; }; @@ -202,7 +164,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011000 0x400>; interrupts = <37>; - clocks = <&clk_pclk2>; + clocks = <&rcc 0 164>; status = "disabled"; }; @@ -210,19 +172,26 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011400 0x400>; interrupts = <71>; - clocks = <&clk_pclk2>; + clocks = <&rcc 0 165>; status = "disabled"; }; rcc: rcc@40023810 { #reset-cells = <1>; - compatible = "st,stm32-rcc"; + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; reg = <0x40023800 0x400>; - }; + clocks = <&clk_hse>; + #clock-cells = <2>; + }; +#if 0 + of_property_read_string_index(dev, "reg-names", "gates"); + index = of_property_read_string_index(dev, "reg-names", "gates"); + of_iomap(np, index); +#endif }; }; &systick { - clocks = <&clk_systick>; + clocks = <&rcc 1 0>; status = "okay"; };