From patchwork Tue May 26 12:49:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjun Guo X-Patchwork-Id: 6479841 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id ABEACC0020 for ; Tue, 26 May 2015 12:54:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 81F1A2060E for ; Tue, 26 May 2015 12:54:03 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0A066204A7 for ; Tue, 26 May 2015 12:54:02 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YxEKV-0004jF-WA; Tue, 26 May 2015 12:51:36 +0000 Received: from mail-pd0-f178.google.com ([209.85.192.178]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YxEJd-0004JE-8m for linux-arm-kernel@lists.infradead.org; Tue, 26 May 2015 12:50:42 +0000 Received: by pdbqa5 with SMTP id qa5so90255548pdb.0 for ; Tue, 26 May 2015 05:50:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ELKGEQfTf7/fqXieW359eUc9GISBd0LXeeM1CZzD69U=; b=flo+WeThSD+UQE4Ph18cHpWEto9mvk5EGSlCa7HPRH7TpaRzgLtOcJwuvnGmoN6rGq Yvw/umibSV3cnA0wD+yKQ/arv+QQAMYQ3UogvYzjb+iTg8ZebqCPTU3tSjU3O3dFQLrd BhYJripLuYejgEgg3iQgp05nUXOqpkEeDfm2mPGw1WDNWpRtjrAtbl5QqvWgaGEGBkQX LmBbfaruTZKY8vl1mUzGM48QoTs8/35VE+bP9PXFWT5yosLVPUCcITUxeXDj/lOIXx3x Wdqxwo9al8EFq33nTvVyc8RdInOytFmS9qq+6bvxEGXsQ6nsKdIiPKihkHDB1+Ew2HJn MA8A== X-Gm-Message-State: ALoCoQm9fosrMklIqHxEdkQdrFwAjG+j5lwwkx/92OdtTcm32RUo6bijVZSgvJBAMCzE9YeUQZ5K X-Received: by 10.70.55.199 with SMTP id u7mr48567306pdp.42.1432644620074; Tue, 26 May 2015 05:50:20 -0700 (PDT) Received: from localhost ([180.150.153.56]) by mx.google.com with ESMTPSA id ue9sm13006264pbc.78.2015.05.26.05.50.18 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 26 May 2015 05:50:19 -0700 (PDT) From: Hanjun Guo To: Bjorn Helgaas , Arnd Bergmann , Catalin Marinas , Will Deacon , "Rafael J. Wysocki" Subject: [PATCH 03/11] x86, pci: Abstract PCI config accessors and use AMD Fam10h workaround exclusively. Date: Tue, 26 May 2015 20:49:16 +0800 Message-Id: <1432644564-24746-4-git-send-email-hanjun.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432644564-24746-1-git-send-email-hanjun.guo@linaro.org> References: <1432644564-24746-1-git-send-email-hanjun.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150526_055041_362108_A138DEFD X-CRM114-Status: GOOD ( 14.71 ) X-Spam-Score: -1.8 (-) Cc: Lorenzo Pieralisi , linaro-acpi@lists.linaro.org, linux-pci@vger.kernel.org, Liviu Dudau , linux-kernel@vger.kernel.org, Tomasz Nowicki , linux-acpi@vger.kernel.org, Hanjun Guo , Suravee Suthikulpanit , Mark Salter , Yijing Wang , Thomas Gleixner , Jiang Liu , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tomasz Nowicki approach. Special MMIO accessors are registered for AMD Fam10h CPUs only. Signed-off-by: Tomasz Nowicki Signed-off-by: Hanjun Guo Tested-by: Suravee Suthikulpanit --- arch/x86/include/asm/pci_x86.h | 8 +++ arch/x86/pci/mmconfig-shared.c | 114 +++++++++++++++++++++++++++++++++++++++++ arch/x86/pci/mmconfig_32.c | 24 +-------- arch/x86/pci/mmconfig_64.c | 24 +-------- arch/x86/pci/numachip.c | 24 +-------- 5 files changed, 128 insertions(+), 66 deletions(-) diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index eddf8f0..f7f3b6a 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -139,6 +139,11 @@ struct pci_mmcfg_region { char name[PCI_MMCFG_RESOURCE_NAME_LEN]; }; +struct pci_mmcfg_mmio_ops { + u32 (*read)(int len, void __iomem *addr); + void (*write)(int len, void __iomem *addr, u32 value); +}; + extern int __init pci_mmcfg_arch_init(void); extern void __init pci_mmcfg_arch_free(void); extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg); @@ -147,6 +152,9 @@ extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, phys_addr_t addr); extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end); extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus); +extern u32 pci_mmio_read(int len, void __iomem *addr); +extern void pci_mmio_write(int len, void __iomem *addr, u32 value); +extern void pci_mmconfig_register_mmio(struct pci_mmcfg_mmio_ops *ops); extern struct list_head pci_mmcfg_list; diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index dd30b7e..8b3bc4f 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -31,6 +31,118 @@ static DEFINE_MUTEX(pci_mmcfg_lock); LIST_HEAD(pci_mmcfg_list); +static u32 +pci_mmconfig_generic_read(int len, void __iomem *addr) +{ + u32 data = 0; + + switch (len) { + case 1: + data = readb(addr); + break; + case 2: + data = readw(addr); + break; + case 4: + data = readl(addr); + break; + } + + return data; +} + +static void +pci_mmconfig_generic_write(int len, void __iomem *addr, u32 value) +{ + switch (len) { + case 1: + writeb(value, addr); + break; + case 2: + writew(value, addr); + break; + case 4: + writel(value, addr); + break; + } +} + +static struct pci_mmcfg_mmio_ops pci_mmcfg_mmio_default = { + .read = pci_mmconfig_generic_read, + .write = pci_mmconfig_generic_write, +}; + +static struct pci_mmcfg_mmio_ops *pci_mmcfg_mmio = &pci_mmcfg_mmio_default; + +static u32 +pci_mmconfig_amd_read(int len, void __iomem *addr) +{ + u32 data = 0; + + switch (len) { + case 1: + data = mmio_config_readb(addr); + break; + case 2: + data = mmio_config_readw(addr); + break; + case 4: + data = mmio_config_readl(addr); + break; + } + + return data; +} + +static void +pci_mmconfig_amd_write(int len, void __iomem *addr, u32 value) +{ + switch (len) { + case 1: + mmio_config_writeb(addr, value); + break; + case 2: + mmio_config_writew(addr, value); + break; + case 4: + mmio_config_writel(addr, value); + break; + } +} + +static struct pci_mmcfg_mmio_ops pci_mmcfg_mmio_amd_fam10h = { + .read = pci_mmconfig_amd_read, + .write = pci_mmconfig_amd_write, +}; + +void +pci_mmconfig_register_mmio(struct pci_mmcfg_mmio_ops *ops) +{ + pci_mmcfg_mmio = ops; +} + +u32 +pci_mmio_read(int len, void __iomem *addr) +{ + if (!pci_mmcfg_mmio) { + pr_err("PCI config space has no accessors !"); + return 0; + } + + return pci_mmcfg_mmio->read(len, addr); +} + +void +pci_mmio_write(int len, void __iomem *addr, u32 value) +{ + if (!pci_mmcfg_mmio) { + pr_err("PCI config space has no accessors !"); + return; + } + + pci_mmcfg_mmio->write(len, addr, value); +} + static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) { if (cfg->res.parent) @@ -231,6 +343,8 @@ static const char *__init pci_mmcfg_amd_fam10h(void) return NULL; } + pci_mmconfig_register_mmio(&pci_mmcfg_mmio_amd_fam10h); + return "AMD Family 10h NB"; } diff --git a/arch/x86/pci/mmconfig_32.c b/arch/x86/pci/mmconfig_32.c index 43984bc..4b3d025 100644 --- a/arch/x86/pci/mmconfig_32.c +++ b/arch/x86/pci/mmconfig_32.c @@ -71,17 +71,7 @@ err: *value = -1; pci_exp_set_dev_base(base, bus, devfn); - switch (len) { - case 1: - *value = mmio_config_readb(mmcfg_virt_addr + reg); - break; - case 2: - *value = mmio_config_readw(mmcfg_virt_addr + reg); - break; - case 4: - *value = mmio_config_readl(mmcfg_virt_addr + reg); - break; - } + *value = pci_mmio_read(len, mmcfg_virt_addr + reg); raw_spin_unlock_irqrestore(&pci_config_lock, flags); rcu_read_unlock(); @@ -108,17 +98,7 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus, pci_exp_set_dev_base(base, bus, devfn); - switch (len) { - case 1: - mmio_config_writeb(mmcfg_virt_addr + reg, value); - break; - case 2: - mmio_config_writew(mmcfg_virt_addr + reg, value); - break; - case 4: - mmio_config_writel(mmcfg_virt_addr + reg, value); - break; - } + pci_mmio_write(len, mmcfg_virt_addr + reg, value); raw_spin_unlock_irqrestore(&pci_config_lock, flags); rcu_read_unlock(); diff --git a/arch/x86/pci/mmconfig_64.c b/arch/x86/pci/mmconfig_64.c index bea5249..032593d 100644 --- a/arch/x86/pci/mmconfig_64.c +++ b/arch/x86/pci/mmconfig_64.c @@ -42,17 +42,7 @@ err: *value = -1; goto err; } - switch (len) { - case 1: - *value = mmio_config_readb(addr + reg); - break; - case 2: - *value = mmio_config_readw(addr + reg); - break; - case 4: - *value = mmio_config_readl(addr + reg); - break; - } + *value = pci_mmio_read(len, addr + reg); rcu_read_unlock(); return 0; @@ -74,17 +64,7 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus, return -EINVAL; } - switch (len) { - case 1: - mmio_config_writeb(addr + reg, value); - break; - case 2: - mmio_config_writew(addr + reg, value); - break; - case 4: - mmio_config_writel(addr + reg, value); - break; - } + pci_mmio_write(len, addr + reg, value); rcu_read_unlock(); return 0; diff --git a/arch/x86/pci/numachip.c b/arch/x86/pci/numachip.c index 2e565e6..5047e9b 100644 --- a/arch/x86/pci/numachip.c +++ b/arch/x86/pci/numachip.c @@ -51,17 +51,7 @@ err: *value = -1; goto err; } - switch (len) { - case 1: - *value = mmio_config_readb(addr + reg); - break; - case 2: - *value = mmio_config_readw(addr + reg); - break; - case 4: - *value = mmio_config_readl(addr + reg); - break; - } + *value = pci_mmio_read(len, addr + reg); rcu_read_unlock(); return 0; @@ -87,17 +77,7 @@ static int pci_mmcfg_write_numachip(unsigned int seg, unsigned int bus, return -EINVAL; } - switch (len) { - case 1: - mmio_config_writeb(addr + reg, value); - break; - case 2: - mmio_config_writew(addr + reg, value); - break; - case 4: - mmio_config_writel(addr + reg, value); - break; - } + pci_mmio_write(len, addr + reg, value); rcu_read_unlock(); return 0;