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client-ip=66.35.236.227; helo=sj-itexedge03.altera.priv.altera.com; Received: from sj-itexedge03.altera.priv.altera.com (66.35.236.227) by BN1AFFO11FD043.mail.protection.outlook.com (10.58.52.190) with Microsoft SMTP Server (TLS) id 15.1.172.14 via Frontend Transport; Tue, 26 May 2015 16:20:26 +0000 Received: from na01-by2-obe.outbound.protection.outlook.com (207.46.163.242) by webmail.altera.com (66.35.236.227) with Microsoft SMTP Server (TLS) id 14.3.174.1; Tue, 26 May 2015 09:18:59 -0700 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=dinguyen@opensource.altera.com; Received: from linux-builds1.altera.com (64.129.157.38) by CY1PR03MB1374.namprd03.prod.outlook.com (10.163.16.28) with Microsoft SMTP Server (TLS) id 15.1.172.22; Tue, 26 May 2015 16:20:22 +0000 From: To: , , , , Subject: [PATCH] ARM: socfpga: dts: enable ethernet for Arria10 devkit Date: Tue, 26 May 2015 11:06:15 -0500 Message-ID: <1432656375-26950-1-git-send-email-dinguyen@opensource.altera.com> X-Mailer: git-send-email 2.2.1 MIME-Version: 1.0 X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: SN1PR07CA0007.namprd07.prod.outlook.com (25.162.170.145) To CY1PR03MB1374.namprd03.prod.outlook.com (25.163.16.28) X-Microsoft-Exchange-Diagnostics-untrusted: 1; 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X-Spam-Score: -1.1 (-) Cc: devicetree@vger.kernel.org, Dinh Nguyen , dinh.linux@gmail.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAD_ENC_HEADER,BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen Update the arria10 gmac nodes with all the necessary properties for ethernet to function on the Arria10 devkit. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 11 +++++++++++ arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 28 ++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 6ceb26e..f5bebdd 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -397,6 +397,7 @@ gmac0: ethernet@ff800000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; reg = <0xff800000 0x2000>; interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; @@ -404,11 +405,16 @@ mac-address = [00 00 00 00 00 00]; snps,multicast-filter-bins = <256>; snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <16384>; + clocks = <&l4_mp_clk>; + clock-names = "stmmaceth"; status = "disabled"; }; gmac1: ethernet@ff802000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; reg = <0xff802000 0x2000>; interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; @@ -418,11 +424,14 @@ snps,perfect-filter-entries = <128>; tx-fifo-depth = <4096>; rx-fifo-depth = <16384>; + clocks = <&l4_mp_clk>; + clock-names = "stmmaceth"; status = "disabled"; }; gmac2: ethernet@ff804000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x4C 0>; reg = <0xff804000 0x2000>; interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; @@ -432,6 +441,8 @@ snps,perfect-filter-entries = <128>; tx-fifo-depth = <4096>; rx-fifo-depth = <16384>; + clocks = <&l4_mp_clk>; + clock-names = "stmmaceth"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 347ca4e..94a0709 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -41,6 +41,34 @@ }; }; +&gmac0 { + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + + /* + * These skews assume the user's FPGA design is adding 600ps of delay + * for TX_CLK on Arria 10. + * + * All skews are offset since hardware skew values for the ksz9031 + * range from a negative skew to a positive skew. + * See the micrel-ksz90x1.txt Documentation file for details. + */ + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + max-frame-size = <3800>; + status = "okay"; +}; + &uart1 { status = "okay"; };