| Message ID | 1433320542-49576-3-git-send-email-wangzhou1@hisilicon.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 03/06/15 09:35, Zhou Wang wrote: > This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete > function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci, > move related operations to dw_pcie_host_init. Also set pp->root_bus_nr = 0 in > each PCIe host driver which is based on pcie-designware. > > I am not very clear about I/O resource management: >> if (global_io_offset < SZ_1M && pp->io_size > 0) { >> pci_ioremap_io(global_io_offset, pp->io_base); >> global_io_offset += SZ_64K; >> pci_add_resource_offset(&res, &pp->io, >> global_io_offset - pp->io_bus_addr); >> } > so just move steps in dw_pcie_setup to dw_pcie_host_init. > > I have compiled the driver with multi_v7_defconfig. However, I don't have > ARM32 PCIe related board to do test. It will be appreciated if someone could > help to test it. I have tested this on a 'Freescale i.MX6 Quad SABRE Lite Board', which also uses a designware pcie host controller (PCI_IMX6). Booted, removed/rescanned the bus, then scanned for wireless access points using the b43 driver. Please note my change below. Tested-by: James Morse <james.morse@arm.com> > diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c > index 2e9f84f..b3f0ac7 100644 > --- a/drivers/pci/host/pcie-designware.c > +++ b/drivers/pci/host/pcie-designware.c > @@ -11,6 +11,7 @@ > * published by the Free Software Foundation. > */ > > +#include <linux/hardirq.h> > #include <linux/irq.h> > #include <linux/irqdomain.h> > #include <linux/kernel.h> > @@ -67,17 +68,10 @@ > #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) > #define PCIE_ATU_UPPER_TARGET 0x91C > > -static struct hw_pci dw_pci; > +static struct pci_ops dw_pcie_ops; > > static unsigned long global_io_offset; > > -static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) > -{ > - BUG_ON(!sys->private_data); > - > - return sys->private_data; > -} > - > int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) > { > *val = readl(addr); > @@ -238,7 +232,7 @@ static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) > static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) > { > int irq, pos0, i; > - struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata); > + struct pcie_port *pp = desc->dev->bus->sysdata; > > pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS, > order_base_2(no_irqs)); > @@ -281,7 +275,7 @@ static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, > { > int irq, pos; > struct msi_msg msg; > - struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata); > + struct pcie_port *pp = pdev->bus->sysdata; > > if (desc->msi_attrib.is_msix) > return -EINVAL; > @@ -310,7 +304,7 @@ static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) > { > struct irq_data *data = irq_get_irq_data(irq); > struct msi_desc *msi = irq_data_get_msi(data); > - struct pcie_port *pp = sys_to_pcie(msi->dev->bus->sysdata); > + struct pcie_port *pp = msi->dev->bus->sysdata; > > clear_irq_range(pp, irq, 1, data->hwirq); > } > @@ -342,13 +336,15 @@ static const struct irq_domain_ops msi_domain_ops = { > .map = dw_pcie_msi_map, > }; > > -int dw_pcie_host_init(struct pcie_port *pp) > +int __init dw_pcie_host_init(struct pcie_port *pp) > { > struct device_node *np = pp->dev->of_node; > struct platform_device *pdev = to_platform_device(pp->dev); > struct of_pci_range range; > struct of_pci_range_parser parser; > + struct pci_bus *bus; > struct resource *cfg_res; > + LIST_HEAD(res); > u32 val, na, ns; > const __be32 *addrp; > int i, index, ret; > @@ -502,15 +498,49 @@ int dw_pcie_host_init(struct pcie_port *pp) > val |= PORT_LOGIC_SPEED_CHANGE; > dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); > > -#ifdef CONFIG_PCI_MSI > - dw_pcie_msi_chip.dev = pp->dev; > - dw_pci.msi_ctrl = &dw_pcie_msi_chip; > +#ifdef CONFIG_ARM > + /* > + * FIXME: we should really be able to use > + * of_pci_get_host_bridge_resources on arm32 as well, > + * but the conversion needs some more testing > + */ > + if (global_io_offset < SZ_1M && pp->io_size > 0) { > + pci_ioremap_io(global_io_offset, pp->io_base); > + global_io_offset += SZ_64K; > + pci_add_resource_offset(&res, &pp->io, > + global_io_offset - pp->io_bus_addr); > + } > + pci_add_resource_offset(&res, &pp->mem, > + pp->mem.start - pp->mem_bus_addr); > + pci_add_resource(&res, &pp->busn); I don't think this #ifdef is necessary. In the spirit of 'the conversion needs some more testing', I removed it leaving just the below arm64 code. This worked on my Freescale i.MX6 Quad SABRE Lite Board, I went as far as scanning for wireless access points. > +#else > + ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base); of_pci_get_host_bridge_resources expects &pp->io_base to be a resource_size_t*, but &io_base is u64*. This generates a warning on arm with the above change. Changing the the type in drivers/pci/host/pcie-designware.h fixes this. Thanks, James > + if (ret) > + return ret; > +#endif > + > + bus = pci_create_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops, > + pp, &res); > + if (!bus) > + return -ENOMEM; > + > +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN > + bus->msi = container_of(&pp->irq_domain, struct msi_controller, domain); > +#else > + bus->msi = &dw_pcie_msi_chip; > #endif > > - dw_pci.nr_controllers = 1; > - dw_pci.private_data = (void **)&pp; > + pci_scan_child_bus(bus); > + if (pp->ops->scan_bus) > + pp->ops->scan_bus(pp); > > - pci_common_init_dev(pp->dev, &dw_pci); > +#ifdef CONFIG_ARM > + /* support old dtbs that incorrectly describe IRQs */ > + pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); > +#endif > + > + pci_assign_unassigned_bus_resources(bus); > + pci_bus_add_devices(bus); > > return 0; > } > @@ -653,7 +683,7 @@ static int dw_pcie_valid_config(struct pcie_port *pp, > static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, > int size, u32 *val) > { > - struct pcie_port *pp = sys_to_pcie(bus->sysdata); > + struct pcie_port *pp = bus->sysdata; > int ret; > > if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { > @@ -677,7 +707,7 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, > static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, > int where, int size, u32 val) > { > - struct pcie_port *pp = sys_to_pcie(bus->sysdata); > + struct pcie_port *pp = bus->sysdata; > int ret; > > if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) > @@ -701,64 +731,6 @@ static struct pci_ops dw_pcie_ops = { > .write = dw_pcie_wr_conf, > }; > > -static int dw_pcie_setup(int nr, struct pci_sys_data *sys) > -{ > - struct pcie_port *pp; > - > - pp = sys_to_pcie(sys); > - > - if (global_io_offset < SZ_1M && pp->io_size > 0) { > - sys->io_offset = global_io_offset - pp->io_bus_addr; > - pci_ioremap_io(global_io_offset, pp->io_base); > - global_io_offset += SZ_64K; > - pci_add_resource_offset(&sys->resources, &pp->io, > - sys->io_offset); > - } > - > - sys->mem_offset = pp->mem.start - pp->mem_bus_addr; > - pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); > - pci_add_resource(&sys->resources, &pp->busn); > - > - return 1; > -} > - > -static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) > -{ > - struct pci_bus *bus; > - struct pcie_port *pp = sys_to_pcie(sys); > - > - pp->root_bus_nr = sys->busnr; > - bus = pci_create_root_bus(pp->dev, sys->busnr, > - &dw_pcie_ops, sys, &sys->resources); > - if (!bus) > - return NULL; > - > - pci_scan_child_bus(bus); > - > - if (bus && pp->ops->scan_bus) > - pp->ops->scan_bus(pp); > - > - return bus; > -} > - > -static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) > -{ > - struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); > - int irq; > - > - irq = of_irq_parse_and_map_pci(dev, slot, pin); > - if (!irq) > - irq = pp->irq; > - > - return irq; > -} > - > -static struct hw_pci dw_pci = { > - .setup = dw_pcie_setup, > - .scan = dw_pcie_scan_bus, > - .map_irq = dw_pcie_map_irq, > -}; > - > void dw_pcie_setup_rc(struct pcie_port *pp) > { > u32 val;
On 2015/6/4 21:19, James Morse wrote: > On 03/06/15 09:35, Zhou Wang wrote: >> This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete >> function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci, >> move related operations to dw_pcie_host_init. Also set pp->root_bus_nr = 0 in >> each PCIe host driver which is based on pcie-designware. >> >> I am not very clear about I/O resource management: >>> if (global_io_offset < SZ_1M && pp->io_size > 0) { >>> pci_ioremap_io(global_io_offset, pp->io_base); >>> global_io_offset += SZ_64K; >>> pci_add_resource_offset(&res, &pp->io, >>> global_io_offset - pp->io_bus_addr); >>> } >> so just move steps in dw_pcie_setup to dw_pcie_host_init. >> >> I have compiled the driver with multi_v7_defconfig. However, I don't have >> ARM32 PCIe related board to do test. It will be appreciated if someone could >> help to test it. > > I have tested this on a 'Freescale i.MX6 Quad SABRE Lite Board', which also > uses a designware pcie host controller (PCI_IMX6). Booted, > removed/rescanned the bus, then scanned for wireless access points using > the b43 driver. Please note my change below. > > Tested-by: James Morse <james.morse@arm.com> > Hi James, Many thanks for your help to test :) >> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c >> index 2e9f84f..b3f0ac7 100644 >> --- a/drivers/pci/host/pcie-designware.c >> +++ b/drivers/pci/host/pcie-designware.c >> @@ -11,6 +11,7 @@ >> * published by the Free Software Foundation. >> */ >> >> +#include <linux/hardirq.h> >> #include <linux/irq.h> >> #include <linux/irqdomain.h> >> #include <linux/kernel.h> >> @@ -67,17 +68,10 @@ >> #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) >> #define PCIE_ATU_UPPER_TARGET 0x91C >> >> -static struct hw_pci dw_pci; >> +static struct pci_ops dw_pcie_ops; >> >> static unsigned long global_io_offset; >> >> -static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) >> -{ >> - BUG_ON(!sys->private_data); >> - >> - return sys->private_data; >> -} >> - >> int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) >> { >> *val = readl(addr); >> @@ -238,7 +232,7 @@ static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) >> static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) >> { >> int irq, pos0, i; >> - struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata); >> + struct pcie_port *pp = desc->dev->bus->sysdata; >> >> pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS, >> order_base_2(no_irqs)); >> @@ -281,7 +275,7 @@ static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, >> { >> int irq, pos; >> struct msi_msg msg; >> - struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata); >> + struct pcie_port *pp = pdev->bus->sysdata; >> >> if (desc->msi_attrib.is_msix) >> return -EINVAL; >> @@ -310,7 +304,7 @@ static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) >> { >> struct irq_data *data = irq_get_irq_data(irq); >> struct msi_desc *msi = irq_data_get_msi(data); >> - struct pcie_port *pp = sys_to_pcie(msi->dev->bus->sysdata); >> + struct pcie_port *pp = msi->dev->bus->sysdata; >> >> clear_irq_range(pp, irq, 1, data->hwirq); >> } >> @@ -342,13 +336,15 @@ static const struct irq_domain_ops msi_domain_ops = { >> .map = dw_pcie_msi_map, >> }; >> >> -int dw_pcie_host_init(struct pcie_port *pp) >> +int __init dw_pcie_host_init(struct pcie_port *pp) >> { >> struct device_node *np = pp->dev->of_node; >> struct platform_device *pdev = to_platform_device(pp->dev); >> struct of_pci_range range; >> struct of_pci_range_parser parser; >> + struct pci_bus *bus; >> struct resource *cfg_res; >> + LIST_HEAD(res); >> u32 val, na, ns; >> const __be32 *addrp; >> int i, index, ret; >> @@ -502,15 +498,49 @@ int dw_pcie_host_init(struct pcie_port *pp) >> val |= PORT_LOGIC_SPEED_CHANGE; >> dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); >> >> -#ifdef CONFIG_PCI_MSI >> - dw_pcie_msi_chip.dev = pp->dev; >> - dw_pci.msi_ctrl = &dw_pcie_msi_chip; >> +#ifdef CONFIG_ARM >> + /* >> + * FIXME: we should really be able to use >> + * of_pci_get_host_bridge_resources on arm32 as well, >> + * but the conversion needs some more testing >> + */ >> + if (global_io_offset < SZ_1M && pp->io_size > 0) { >> + pci_ioremap_io(global_io_offset, pp->io_base); >> + global_io_offset += SZ_64K; >> + pci_add_resource_offset(&res, &pp->io, >> + global_io_offset - pp->io_bus_addr); >> + } >> + pci_add_resource_offset(&res, &pp->mem, >> + pp->mem.start - pp->mem_bus_addr); >> + pci_add_resource(&res, &pp->busn); > > I don't think this #ifdef is necessary. In the spirit of 'the conversion > needs some more testing', I removed it leaving just the below arm64 code. > > This worked on my Freescale i.MX6 Quad SABRE Lite Board, I went as far as > scanning for wireless access points. > I think it depends on which kind of PCIe device you use, if we use a PCIe device with a I/O Bar, it may not work well without above code. But so far, I have not met a PCIe device which must work with a I/O Bar. >> +#else >> + ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base); > > of_pci_get_host_bridge_resources expects &pp->io_base to be a > resource_size_t*, but &io_base is u64*. This generates a warning on arm > with the above change. Changing the the type in > drivers/pci/host/pcie-designware.h fixes this. > > > Thanks, > > James > OK, will modify this in next version. Best Regards and thanks again for your test, Zhou >> + if (ret) >> + return ret; >> +#endif >> + >> + bus = pci_create_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops, >> + pp, &res); >> + if (!bus) >> + return -ENOMEM; >> + >> +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN >> + bus->msi = container_of(&pp->irq_domain, struct msi_controller, domain); >> +#else >> + bus->msi = &dw_pcie_msi_chip; >> #endif >> >> - dw_pci.nr_controllers = 1; >> - dw_pci.private_data = (void **)&pp; >> + pci_scan_child_bus(bus); >> + if (pp->ops->scan_bus) >> + pp->ops->scan_bus(pp); >> >> - pci_common_init_dev(pp->dev, &dw_pci); >> +#ifdef CONFIG_ARM >> + /* support old dtbs that incorrectly describe IRQs */ >> + pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); >> +#endif >> + >> + pci_assign_unassigned_bus_resources(bus); >> + pci_bus_add_devices(bus); >> >> return 0; >> } >> @@ -653,7 +683,7 @@ static int dw_pcie_valid_config(struct pcie_port *pp, >> static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, >> int size, u32 *val) >> { >> - struct pcie_port *pp = sys_to_pcie(bus->sysdata); >> + struct pcie_port *pp = bus->sysdata; >> int ret; >> >> if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { >> @@ -677,7 +707,7 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, >> static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, >> int where, int size, u32 val) >> { >> - struct pcie_port *pp = sys_to_pcie(bus->sysdata); >> + struct pcie_port *pp = bus->sysdata; >> int ret; >> >> if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) >> @@ -701,64 +731,6 @@ static struct pci_ops dw_pcie_ops = { >> .write = dw_pcie_wr_conf, >> }; >> >> -static int dw_pcie_setup(int nr, struct pci_sys_data *sys) >> -{ >> - struct pcie_port *pp; >> - >> - pp = sys_to_pcie(sys); >> - >> - if (global_io_offset < SZ_1M && pp->io_size > 0) { >> - sys->io_offset = global_io_offset - pp->io_bus_addr; >> - pci_ioremap_io(global_io_offset, pp->io_base); >> - global_io_offset += SZ_64K; >> - pci_add_resource_offset(&sys->resources, &pp->io, >> - sys->io_offset); >> - } >> - >> - sys->mem_offset = pp->mem.start - pp->mem_bus_addr; >> - pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); >> - pci_add_resource(&sys->resources, &pp->busn); >> - >> - return 1; >> -} >> - >> -static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) >> -{ >> - struct pci_bus *bus; >> - struct pcie_port *pp = sys_to_pcie(sys); >> - >> - pp->root_bus_nr = sys->busnr; >> - bus = pci_create_root_bus(pp->dev, sys->busnr, >> - &dw_pcie_ops, sys, &sys->resources); >> - if (!bus) >> - return NULL; >> - >> - pci_scan_child_bus(bus); >> - >> - if (bus && pp->ops->scan_bus) >> - pp->ops->scan_bus(pp); >> - >> - return bus; >> -} >> - >> -static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) >> -{ >> - struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); >> - int irq; >> - >> - irq = of_irq_parse_and_map_pci(dev, slot, pin); >> - if (!irq) >> - irq = pp->irq; >> - >> - return irq; >> -} >> - >> -static struct hw_pci dw_pci = { >> - .setup = dw_pcie_setup, >> - .scan = dw_pcie_scan_bus, >> - .map_irq = dw_pcie_map_irq, >> -}; >> - >> void dw_pcie_setup_rc(struct pcie_port *pp) >> { >> u32 val; > > > . >
On Fri, Jun 05, 2015 at 09:11:30AM +0100, Zhou Wang wrote: [...] > >> -int dw_pcie_host_init(struct pcie_port *pp) > >> +int __init dw_pcie_host_init(struct pcie_port *pp) > >> { > >> struct device_node *np = pp->dev->of_node; > >> struct platform_device *pdev = to_platform_device(pp->dev); > >> struct of_pci_range range; > >> struct of_pci_range_parser parser; > >> + struct pci_bus *bus; > >> struct resource *cfg_res; > >> + LIST_HEAD(res); > >> u32 val, na, ns; > >> const __be32 *addrp; > >> int i, index, ret; > >> @@ -502,15 +498,49 @@ int dw_pcie_host_init(struct pcie_port *pp) > >> val |= PORT_LOGIC_SPEED_CHANGE; > >> dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); > >> > >> -#ifdef CONFIG_PCI_MSI > >> - dw_pcie_msi_chip.dev = pp->dev; > >> - dw_pci.msi_ctrl = &dw_pcie_msi_chip; > >> +#ifdef CONFIG_ARM > >> + /* > >> + * FIXME: we should really be able to use > >> + * of_pci_get_host_bridge_resources on arm32 as well, > >> + * but the conversion needs some more testing > >> + */ > >> + if (global_io_offset < SZ_1M && pp->io_size > 0) { > >> + pci_ioremap_io(global_io_offset, pp->io_base); > >> + global_io_offset += SZ_64K; > >> + pci_add_resource_offset(&res, &pp->io, > >> + global_io_offset - pp->io_bus_addr); > >> + } > >> + pci_add_resource_offset(&res, &pp->mem, > >> + pp->mem.start - pp->mem_bus_addr); > >> + pci_add_resource(&res, &pp->busn); > > > > I don't think this #ifdef is necessary. In the spirit of 'the conversion > > needs some more testing', I removed it leaving just the below arm64 code. > > > > This worked on my Freescale i.MX6 Quad SABRE Lite Board, I went as far as > > scanning for wireless access points. > > > > I think it depends on which kind of PCIe device you use, if we use a PCIe device > with a I/O Bar, it may not work well without above code. But so far, I have not > met a PCIe device which must work with a I/O Bar. There are two problems here: 1) the io_base address you get from of_pci_get_host_bridge_resources must be mapped using pci_remap_iospace. You are not doing this, so even if you had a PCIe card with I/O bar it would not work on arm64 as the code stands. Remember that I/O space on arm/arm64 works as a memory access with offset from PCI_IOBASE and that's the value you get in the I/O resource. See: drivers/pci/host/pci-host-generic.c drivers/pci/host/pci-versatile.c drivers/pci/host/pci-xgene.c 2) (1) above would sort out I/O space access for both arm and arm64 so, as James said, the #ifdef is useless. I hope this makes things clearer. Thanks, Lorenzo > > >> +#else > >> + ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base); > > > > of_pci_get_host_bridge_resources expects &pp->io_base to be a > > resource_size_t*, but &io_base is u64*. This generates a warning on arm > > with the above change. Changing the the type in > > drivers/pci/host/pcie-designware.h fixes this. > > > > > > Thanks, > > > > James > > > > OK, will modify this in next version. > > Best Regards and thanks again for your test, > Zhou > > >> + if (ret) > >> + return ret; > >> +#endif > >> + > >> + bus = pci_create_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops, > >> + pp, &res); > >> + if (!bus) > >> + return -ENOMEM; > >> + > >> +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN > >> + bus->msi = container_of(&pp->irq_domain, struct msi_controller, domain); > >> +#else > >> + bus->msi = &dw_pcie_msi_chip; > >> #endif > >> > >> - dw_pci.nr_controllers = 1; > >> - dw_pci.private_data = (void **)&pp; > >> + pci_scan_child_bus(bus); > >> + if (pp->ops->scan_bus) > >> + pp->ops->scan_bus(pp); > >> > >> - pci_common_init_dev(pp->dev, &dw_pci); > >> +#ifdef CONFIG_ARM > >> + /* support old dtbs that incorrectly describe IRQs */ > >> + pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); > >> +#endif > >> + > >> + pci_assign_unassigned_bus_resources(bus); > >> + pci_bus_add_devices(bus); > >> > >> return 0; > >> } > >> @@ -653,7 +683,7 @@ static int dw_pcie_valid_config(struct pcie_port *pp, > >> static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, > >> int size, u32 *val) > >> { > >> - struct pcie_port *pp = sys_to_pcie(bus->sysdata); > >> + struct pcie_port *pp = bus->sysdata; > >> int ret; > >> > >> if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { > >> @@ -677,7 +707,7 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, > >> static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, > >> int where, int size, u32 val) > >> { > >> - struct pcie_port *pp = sys_to_pcie(bus->sysdata); > >> + struct pcie_port *pp = bus->sysdata; > >> int ret; > >> > >> if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) > >> @@ -701,64 +731,6 @@ static struct pci_ops dw_pcie_ops = { > >> .write = dw_pcie_wr_conf, > >> }; > >> > >> -static int dw_pcie_setup(int nr, struct pci_sys_data *sys) > >> -{ > >> - struct pcie_port *pp; > >> - > >> - pp = sys_to_pcie(sys); > >> - > >> - if (global_io_offset < SZ_1M && pp->io_size > 0) { > >> - sys->io_offset = global_io_offset - pp->io_bus_addr; > >> - pci_ioremap_io(global_io_offset, pp->io_base); > >> - global_io_offset += SZ_64K; > >> - pci_add_resource_offset(&sys->resources, &pp->io, > >> - sys->io_offset); > >> - } > >> - > >> - sys->mem_offset = pp->mem.start - pp->mem_bus_addr; > >> - pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); > >> - pci_add_resource(&sys->resources, &pp->busn); > >> - > >> - return 1; > >> -} > >> - > >> -static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) > >> -{ > >> - struct pci_bus *bus; > >> - struct pcie_port *pp = sys_to_pcie(sys); > >> - > >> - pp->root_bus_nr = sys->busnr; > >> - bus = pci_create_root_bus(pp->dev, sys->busnr, > >> - &dw_pcie_ops, sys, &sys->resources); > >> - if (!bus) > >> - return NULL; > >> - > >> - pci_scan_child_bus(bus); > >> - > >> - if (bus && pp->ops->scan_bus) > >> - pp->ops->scan_bus(pp); > >> - > >> - return bus; > >> -} > >> - > >> -static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) > >> -{ > >> - struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); > >> - int irq; > >> - > >> - irq = of_irq_parse_and_map_pci(dev, slot, pin); > >> - if (!irq) > >> - irq = pp->irq; > >> - > >> - return irq; > >> -} > >> - > >> -static struct hw_pci dw_pci = { > >> - .setup = dw_pcie_setup, > >> - .scan = dw_pcie_scan_bus, > >> - .map_irq = dw_pcie_map_irq, > >> -}; > >> - > >> void dw_pcie_setup_rc(struct pcie_port *pp) > >> { > >> u32 val; > > > > > > . > > > > > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html >
On 2015/6/4 21:19, James Morse wrote: > On 03/06/15 09:35, Zhou Wang wrote: >> This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete >> function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci, >> move related operations to dw_pcie_host_init. Also set pp->root_bus_nr = 0 in >> each PCIe host driver which is based on pcie-designware. >> >> I am not very clear about I/O resource management: >>> if (global_io_offset < SZ_1M && pp->io_size > 0) { >>> pci_ioremap_io(global_io_offset, pp->io_base); >>> global_io_offset += SZ_64K; >>> pci_add_resource_offset(&res, &pp->io, >>> global_io_offset - pp->io_bus_addr); >>> } >> so just move steps in dw_pcie_setup to dw_pcie_host_init. >> >> I have compiled the driver with multi_v7_defconfig. However, I don't have >> ARM32 PCIe related board to do test. It will be appreciated if someone could >> help to test it. > > I have tested this on a 'Freescale i.MX6 Quad SABRE Lite Board', which also > uses a designware pcie host controller (PCI_IMX6). Booted, > removed/rescanned the bus, then scanned for wireless access points using > the b43 driver. Please note my change below. > > Tested-by: James Morse <james.morse@arm.com> > >> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c >> index 2e9f84f..b3f0ac7 100644 >> --- a/drivers/pci/host/pcie-designware.c >> +++ b/drivers/pci/host/pcie-designware.c >> @@ -11,6 +11,7 @@ >> * published by the Free Software Foundation. >> */ >> >> +#include <linux/hardirq.h> >> #include <linux/irq.h> >> #include <linux/irqdomain.h> >> #include <linux/kernel.h> >> @@ -67,17 +68,10 @@ >> #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) >> #define PCIE_ATU_UPPER_TARGET 0x91C >> >> -static struct hw_pci dw_pci; >> +static struct pci_ops dw_pcie_ops; >> >> static unsigned long global_io_offset; >> >> -static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) >> -{ >> - BUG_ON(!sys->private_data); >> - >> - return sys->private_data; >> -} >> - >> int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) >> { >> *val = readl(addr); >> @@ -238,7 +232,7 @@ static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) >> static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) >> { >> int irq, pos0, i; >> - struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata); >> + struct pcie_port *pp = desc->dev->bus->sysdata; >> >> pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS, >> order_base_2(no_irqs)); >> @@ -281,7 +275,7 @@ static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, >> { >> int irq, pos; >> struct msi_msg msg; >> - struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata); >> + struct pcie_port *pp = pdev->bus->sysdata; >> >> if (desc->msi_attrib.is_msix) >> return -EINVAL; >> @@ -310,7 +304,7 @@ static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) >> { >> struct irq_data *data = irq_get_irq_data(irq); >> struct msi_desc *msi = irq_data_get_msi(data); >> - struct pcie_port *pp = sys_to_pcie(msi->dev->bus->sysdata); >> + struct pcie_port *pp = msi->dev->bus->sysdata; >> >> clear_irq_range(pp, irq, 1, data->hwirq); >> } >> @@ -342,13 +336,15 @@ static const struct irq_domain_ops msi_domain_ops = { >> .map = dw_pcie_msi_map, >> }; >> >> -int dw_pcie_host_init(struct pcie_port *pp) >> +int __init dw_pcie_host_init(struct pcie_port *pp) >> { >> struct device_node *np = pp->dev->of_node; >> struct platform_device *pdev = to_platform_device(pp->dev); >> struct of_pci_range range; >> struct of_pci_range_parser parser; >> + struct pci_bus *bus; >> struct resource *cfg_res; >> + LIST_HEAD(res); >> u32 val, na, ns; >> const __be32 *addrp; >> int i, index, ret; >> @@ -502,15 +498,49 @@ int dw_pcie_host_init(struct pcie_port *pp) >> val |= PORT_LOGIC_SPEED_CHANGE; >> dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); >> >> -#ifdef CONFIG_PCI_MSI >> - dw_pcie_msi_chip.dev = pp->dev; >> - dw_pci.msi_ctrl = &dw_pcie_msi_chip; >> +#ifdef CONFIG_ARM >> + /* >> + * FIXME: we should really be able to use >> + * of_pci_get_host_bridge_resources on arm32 as well, >> + * but the conversion needs some more testing >> + */ >> + if (global_io_offset < SZ_1M && pp->io_size > 0) { >> + pci_ioremap_io(global_io_offset, pp->io_base); >> + global_io_offset += SZ_64K; >> + pci_add_resource_offset(&res, &pp->io, >> + global_io_offset - pp->io_bus_addr); >> + } >> + pci_add_resource_offset(&res, &pp->mem, >> + pp->mem.start - pp->mem_bus_addr); >> + pci_add_resource(&res, &pp->busn); > > I don't think this #ifdef is necessary. In the spirit of 'the conversion > needs some more testing', I removed it leaving just the below arm64 code. > > This worked on my Freescale i.MX6 Quad SABRE Lite Board, I went as far as > scanning for wireless access points. > > Hi James, I think you are right. We can remove #ifdef as of_pci_get_host_bridge_resources also manages mem, io and bus resources. And just as Lorenzo said, if we want PCIe cards with IO bar work well, pci_remap_iospace should be added after of_pci_get_host_bridge_resources to map IO cpu address to PCI_IOBASE. Thanks again for your test :) Zhou >> +#else >> + ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base); > > of_pci_get_host_bridge_resources expects &pp->io_base to be a > resource_size_t*, but &io_base is u64*. This generates a warning on arm > with the above change. Changing the the type in > drivers/pci/host/pcie-designware.h fixes this. > > > Thanks, > > James > >> + if (ret) >> + return ret; >> +#endif >> + >> + bus = pci_create_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops, >> + pp, &res); >> + if (!bus) >> + return -ENOMEM; >> + >> +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN >> + bus->msi = container_of(&pp->irq_domain, struct msi_controller, domain); >> +#else >> + bus->msi = &dw_pcie_msi_chip; >> #endif >> >> - dw_pci.nr_controllers = 1; >> - dw_pci.private_data = (void **)&pp; >> + pci_scan_child_bus(bus); >> + if (pp->ops->scan_bus) >> + pp->ops->scan_bus(pp); >> >> - pci_common_init_dev(pp->dev, &dw_pci); >> +#ifdef CONFIG_ARM >> + /* support old dtbs that incorrectly describe IRQs */ >> + pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); >> +#endif >> + >> + pci_assign_unassigned_bus_resources(bus); >> + pci_bus_add_devices(bus); >> >> return 0; >> } >> @@ -653,7 +683,7 @@ static int dw_pcie_valid_config(struct pcie_port *pp, >> static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, >> int size, u32 *val) >> { >> - struct pcie_port *pp = sys_to_pcie(bus->sysdata); >> + struct pcie_port *pp = bus->sysdata; >> int ret; >> >> if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { >> @@ -677,7 +707,7 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, >> static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, >> int where, int size, u32 val) >> { >> - struct pcie_port *pp = sys_to_pcie(bus->sysdata); >> + struct pcie_port *pp = bus->sysdata; >> int ret; >> >> if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) >> @@ -701,64 +731,6 @@ static struct pci_ops dw_pcie_ops = { >> .write = dw_pcie_wr_conf, >> }; >> >> -static int dw_pcie_setup(int nr, struct pci_sys_data *sys) >> -{ >> - struct pcie_port *pp; >> - >> - pp = sys_to_pcie(sys); >> - >> - if (global_io_offset < SZ_1M && pp->io_size > 0) { >> - sys->io_offset = global_io_offset - pp->io_bus_addr; >> - pci_ioremap_io(global_io_offset, pp->io_base); >> - global_io_offset += SZ_64K; >> - pci_add_resource_offset(&sys->resources, &pp->io, >> - sys->io_offset); >> - } >> - >> - sys->mem_offset = pp->mem.start - pp->mem_bus_addr; >> - pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); >> - pci_add_resource(&sys->resources, &pp->busn); >> - >> - return 1; >> -} >> - >> -static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) >> -{ >> - struct pci_bus *bus; >> - struct pcie_port *pp = sys_to_pcie(sys); >> - >> - pp->root_bus_nr = sys->busnr; >> - bus = pci_create_root_bus(pp->dev, sys->busnr, >> - &dw_pcie_ops, sys, &sys->resources); >> - if (!bus) >> - return NULL; >> - >> - pci_scan_child_bus(bus); >> - >> - if (bus && pp->ops->scan_bus) >> - pp->ops->scan_bus(pp); >> - >> - return bus; >> -} >> - >> -static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) >> -{ >> - struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); >> - int irq; >> - >> - irq = of_irq_parse_and_map_pci(dev, slot, pin); >> - if (!irq) >> - irq = pp->irq; >> - >> - return irq; >> -} >> - >> -static struct hw_pci dw_pci = { >> - .setup = dw_pcie_setup, >> - .scan = dw_pcie_scan_bus, >> - .map_irq = dw_pcie_map_irq, >> -}; >> - >> void dw_pcie_setup_rc(struct pcie_port *pp) >> { >> u32 val; > > > . >
On 2015/6/9 19:15, Lorenzo Pieralisi wrote: > On Fri, Jun 05, 2015 at 09:11:30AM +0100, Zhou Wang wrote: > > [...] > >>>> -int dw_pcie_host_init(struct pcie_port *pp) >>>> +int __init dw_pcie_host_init(struct pcie_port *pp) >>>> { >>>> struct device_node *np = pp->dev->of_node; >>>> struct platform_device *pdev = to_platform_device(pp->dev); >>>> struct of_pci_range range; >>>> struct of_pci_range_parser parser; >>>> + struct pci_bus *bus; >>>> struct resource *cfg_res; >>>> + LIST_HEAD(res); >>>> u32 val, na, ns; >>>> const __be32 *addrp; >>>> int i, index, ret; >>>> @@ -502,15 +498,49 @@ int dw_pcie_host_init(struct pcie_port *pp) >>>> val |= PORT_LOGIC_SPEED_CHANGE; >>>> dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); >>>> >>>> -#ifdef CONFIG_PCI_MSI >>>> - dw_pcie_msi_chip.dev = pp->dev; >>>> - dw_pci.msi_ctrl = &dw_pcie_msi_chip; >>>> +#ifdef CONFIG_ARM >>>> + /* >>>> + * FIXME: we should really be able to use >>>> + * of_pci_get_host_bridge_resources on arm32 as well, >>>> + * but the conversion needs some more testing >>>> + */ >>>> + if (global_io_offset < SZ_1M && pp->io_size > 0) { >>>> + pci_ioremap_io(global_io_offset, pp->io_base); >>>> + global_io_offset += SZ_64K; >>>> + pci_add_resource_offset(&res, &pp->io, >>>> + global_io_offset - pp->io_bus_addr); >>>> + } >>>> + pci_add_resource_offset(&res, &pp->mem, >>>> + pp->mem.start - pp->mem_bus_addr); >>>> + pci_add_resource(&res, &pp->busn); >>> >>> I don't think this #ifdef is necessary. In the spirit of 'the conversion >>> needs some more testing', I removed it leaving just the below arm64 code. >>> >>> This worked on my Freescale i.MX6 Quad SABRE Lite Board, I went as far as >>> scanning for wireless access points. >>> >> >> I think it depends on which kind of PCIe device you use, if we use a PCIe device >> with a I/O Bar, it may not work well without above code. But so far, I have not >> met a PCIe device which must work with a I/O Bar. > > There are two problems here: > > 1) the io_base address you get from of_pci_get_host_bridge_resources > must be mapped using pci_remap_iospace. You are not doing this, so > even if you had a PCIe card with I/O bar it would not work on arm64 > as the code stands. Remember that I/O space on arm/arm64 works as a > memory access with offset from PCI_IOBASE and that's the value you get > in the I/O resource. See: > > drivers/pci/host/pci-host-generic.c > drivers/pci/host/pci-versatile.c > drivers/pci/host/pci-xgene.c > > 2) (1) above would sort out I/O space access for both arm and arm64 so, > as James said, the #ifdef is useless. > > I hope this makes things clearer. > > Thanks, > Lorenzo > Hi Lorenzo, Many thanks for your explanation. I have a better understanding now. So I think we could remove #ifdef and add pci_remap_iospace after of_pci_get_host_bridge_resources. Regards, Zhou >> >>>> +#else >>>> + ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base); >>> >>> of_pci_get_host_bridge_resources expects &pp->io_base to be a >>> resource_size_t*, but &io_base is u64*. This generates a warning on arm >>> with the above change. Changing the the type in >>> drivers/pci/host/pcie-designware.h fixes this. >>> >>> >>> Thanks, >>> >>> James >>> >> >> OK, will modify this in next version. >> >> Best Regards and thanks again for your test, >> Zhou >> >>>> + if (ret) >>>> + return ret; >>>> +#endif >>>> + >>>> + bus = pci_create_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops, >>>> + pp, &res); >>>> + if (!bus) >>>> + return -ENOMEM; >>>> + >>>> +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN >>>> + bus->msi = container_of(&pp->irq_domain, struct msi_controller, domain); >>>> +#else >>>> + bus->msi = &dw_pcie_msi_chip; >>>> #endif >>>> >>>> - dw_pci.nr_controllers = 1; >>>> - dw_pci.private_data = (void **)&pp; >>>> + pci_scan_child_bus(bus); >>>> + if (pp->ops->scan_bus) >>>> + pp->ops->scan_bus(pp); >>>> >>>> - pci_common_init_dev(pp->dev, &dw_pci); >>>> +#ifdef CONFIG_ARM >>>> + /* support old dtbs that incorrectly describe IRQs */ >>>> + pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); >>>> +#endif >>>> + >>>> + pci_assign_unassigned_bus_resources(bus); >>>> + pci_bus_add_devices(bus); >>>> >>>> return 0; >>>> } >>>> @@ -653,7 +683,7 @@ static int dw_pcie_valid_config(struct pcie_port *pp, >>>> static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, >>>> int size, u32 *val) >>>> { >>>> - struct pcie_port *pp = sys_to_pcie(bus->sysdata); >>>> + struct pcie_port *pp = bus->sysdata; >>>> int ret; >>>> >>>> if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { >>>> @@ -677,7 +707,7 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, >>>> static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, >>>> int where, int size, u32 val) >>>> { >>>> - struct pcie_port *pp = sys_to_pcie(bus->sysdata); >>>> + struct pcie_port *pp = bus->sysdata; >>>> int ret; >>>> >>>> if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) >>>> @@ -701,64 +731,6 @@ static struct pci_ops dw_pcie_ops = { >>>> .write = dw_pcie_wr_conf, >>>> }; >>>> >>>> -static int dw_pcie_setup(int nr, struct pci_sys_data *sys) >>>> -{ >>>> - struct pcie_port *pp; >>>> - >>>> - pp = sys_to_pcie(sys); >>>> - >>>> - if (global_io_offset < SZ_1M && pp->io_size > 0) { >>>> - sys->io_offset = global_io_offset - pp->io_bus_addr; >>>> - pci_ioremap_io(global_io_offset, pp->io_base); >>>> - global_io_offset += SZ_64K; >>>> - pci_add_resource_offset(&sys->resources, &pp->io, >>>> - sys->io_offset); >>>> - } >>>> - >>>> - sys->mem_offset = pp->mem.start - pp->mem_bus_addr; >>>> - pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); >>>> - pci_add_resource(&sys->resources, &pp->busn); >>>> - >>>> - return 1; >>>> -} >>>> - >>>> -static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) >>>> -{ >>>> - struct pci_bus *bus; >>>> - struct pcie_port *pp = sys_to_pcie(sys); >>>> - >>>> - pp->root_bus_nr = sys->busnr; >>>> - bus = pci_create_root_bus(pp->dev, sys->busnr, >>>> - &dw_pcie_ops, sys, &sys->resources); >>>> - if (!bus) >>>> - return NULL; >>>> - >>>> - pci_scan_child_bus(bus); >>>> - >>>> - if (bus && pp->ops->scan_bus) >>>> - pp->ops->scan_bus(pp); >>>> - >>>> - return bus; >>>> -} >>>> - >>>> -static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) >>>> -{ >>>> - struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); >>>> - int irq; >>>> - >>>> - irq = of_irq_parse_and_map_pci(dev, slot, pin); >>>> - if (!irq) >>>> - irq = pp->irq; >>>> - >>>> - return irq; >>>> -} >>>> - >>>> -static struct hw_pci dw_pci = { >>>> - .setup = dw_pcie_setup, >>>> - .scan = dw_pcie_scan_bus, >>>> - .map_irq = dw_pcie_map_irq, >>>> -}; >>>> - >>>> void dw_pcie_setup_rc(struct pcie_port *pp) >>>> { >>>> u32 val; >>> >>> >>> . >>> >> >> >> -- >> To unsubscribe from this list: send the line "unsubscribe linux-pci" in >> the body of a message to majordomo@vger.kernel.org >> More majordomo info at http://vger.kernel.org/majordomo-info.html >> > > . >
Hi Zhou Wang, Thanks for unifying arm and arm64 code. On Wed, Jun 3, 2015 at 2:05 PM, Zhou Wang <wangzhou1@hisilicon.com> wrote: > > This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete > function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci, > move related operations to dw_pcie_host_init. Also set pp->root_bus_nr = 0 in > each PCIe host driver which is based on pcie-designware. > > I am not very clear about I/O resource management: Following discussion may help to understand it, specially in the context of designware. http://marc.info/?l=linux-pci&m=138621989417562&w=2 > > if (global_io_offset < SZ_1M && pp->io_size > 0) { > > pci_ioremap_io(global_io_offset, pp->io_base); > > global_io_offset += SZ_64K; > > pci_add_resource_offset(&res, &pp->io, > > global_io_offset - pp->io_bus_addr); > > } > so just move steps in dw_pcie_setup to dw_pcie_host_init. > > I have compiled the driver with multi_v7_defconfig. However, I don't have > ARM32 PCIe related board to do test. It will be appreciated if someone could > help to test it. > > Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> > Tested-by: Fabrice Gasnier <fabrice.gasnier@st.com> > --- > drivers/pci/host/pci-dra7xx.c | 1 + > drivers/pci/host/pci-exynos.c | 2 +- > drivers/pci/host/pci-imx6.c | 2 +- > drivers/pci/host/pci-keystone.c | 2 +- > drivers/pci/host/pci-layerscape.c | 2 +- > drivers/pci/host/pcie-designware.c | 128 +++++++++++++++---------------------- > drivers/pci/host/pcie-spear13xx.c | 2 +- > 7 files changed, 56 insertions(+), 83 deletions(-) > [...] > diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c > index 4a6e62f..5c7a9c4 100644 > --- a/drivers/pci/host/pci-layerscape.c > +++ b/drivers/pci/host/pci-layerscape.c > @@ -101,7 +101,7 @@ static int ls_add_pcie_port(struct ls_pcie *pcie) > pp = &pcie->pp; > pp->dev = pcie->dev; > pp->dbi_base = pcie->dbi; > - pp->root_bus_nr = -1; > + pp->root_bus_nr = 0; similar change for pcie-spear13xx.c should be needed as well. > pp->ops = &ls_pcie_host_ops; > > ret = dw_pcie_host_init(pp); > diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c > index 2e9f84f..b3f0ac7 100644 > --- a/drivers/pci/host/pcie-designware.c > +++ b/drivers/pci/host/pcie-designware.c [...] > -#ifdef CONFIG_PCI_MSI > - dw_pcie_msi_chip.dev = pp->dev; > - dw_pci.msi_ctrl = &dw_pcie_msi_chip; > +#ifdef CONFIG_ARM > + /* > + * FIXME: we should really be able to use > + * of_pci_get_host_bridge_resources on arm32 as well, > + * but the conversion needs some more testing > + */ > + if (global_io_offset < SZ_1M && pp->io_size > 0) { > + pci_ioremap_io(global_io_offset, pp->io_base); > + global_io_offset += SZ_64K; > + pci_add_resource_offset(&res, &pp->io, > + global_io_offset - pp->io_bus_addr); > + } > + pci_add_resource_offset(&res, &pp->mem, > + pp->mem.start - pp->mem_bus_addr); > + pci_add_resource(&res, &pp->busn); > +#else > + ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base); > + if (ret) > + return ret; > +#endif > + > + bus = pci_create_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops, > + pp, &res); > + if (!bus) > + return -ENOMEM; > + > +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN > + bus->msi = container_of(&pp->irq_domain, struct msi_controller, domain); > +#else > + bus->msi = &dw_pcie_msi_chip; > #endif > > - dw_pci.nr_controllers = 1; > - dw_pci.private_data = (void **)&pp; > + pci_scan_child_bus(bus); > + if (pp->ops->scan_bus) > + pp->ops->scan_bus(pp); > > - pci_common_init_dev(pp->dev, &dw_pci); > +#ifdef CONFIG_ARM > + /* support old dtbs that incorrectly describe IRQs */ > + pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); > +#endif > + > + pci_assign_unassigned_bus_resources(bus); > + pci_bus_add_devices(bus); As James and Lorenzo has suggested, of_pci_get_host_bridge_resources should work for ARM as well. I would suggest to move that just after cfg resource parsing and then to remove following piece of code. for_each_of_pci_range(&parser, &range) { ... } ret = of_pci_parse_bus_range(np, &pp->busn); Then you can have a loop like list_for_each_entry(entry, &res, node) { struct resource *res_temp = entry->res; if (resource_type(res_temp) == IORESOURCE_IO) { } else if (resource_type(res_temp) == IORESOURCE_MEM) { } } where you can fill, xx_size, xx_bus_addr, xx_mod_base etc. You can also remove global_io_offset variable. ~Pratyush
Hi Pratyush, sorry for late. On 2015/6/15 3:18, Pratyush Anand wrote: > Hi Zhou Wang, > > Thanks for unifying arm and arm64 code. > > On Wed, Jun 3, 2015 at 2:05 PM, Zhou Wang <wangzhou1@hisilicon.com> wrote: >> >> This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete >> function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci, >> move related operations to dw_pcie_host_init. Also set pp->root_bus_nr = 0 in >> each PCIe host driver which is based on pcie-designware. >> >> I am not very clear about I/O resource management: > > Following discussion may help to understand it, specially in the > context of designware. > > http://marc.info/?l=linux-pci&m=138621989417562&w=2 Thanks for sharing above information. > > >>> if (global_io_offset < SZ_1M && pp->io_size > 0) { >>> pci_ioremap_io(global_io_offset, pp->io_base); >>> global_io_offset += SZ_64K; >>> pci_add_resource_offset(&res, &pp->io, >>> global_io_offset - pp->io_bus_addr); >>> } >> so just move steps in dw_pcie_setup to dw_pcie_host_init. >> >> I have compiled the driver with multi_v7_defconfig. However, I don't have >> ARM32 PCIe related board to do test. It will be appreciated if someone could >> help to test it. >> >> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> >> Tested-by: Fabrice Gasnier <fabrice.gasnier@st.com> >> --- >> drivers/pci/host/pci-dra7xx.c | 1 + >> drivers/pci/host/pci-exynos.c | 2 +- >> drivers/pci/host/pci-imx6.c | 2 +- >> drivers/pci/host/pci-keystone.c | 2 +- >> drivers/pci/host/pci-layerscape.c | 2 +- >> drivers/pci/host/pcie-designware.c | 128 +++++++++++++++---------------------- >> drivers/pci/host/pcie-spear13xx.c | 2 +- >> 7 files changed, 56 insertions(+), 83 deletions(-) >> > > [...] > >> diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c >> index 4a6e62f..5c7a9c4 100644 >> --- a/drivers/pci/host/pci-layerscape.c >> +++ b/drivers/pci/host/pci-layerscape.c >> @@ -101,7 +101,7 @@ static int ls_add_pcie_port(struct ls_pcie *pcie) >> pp = &pcie->pp; >> pp->dev = pcie->dev; >> pp->dbi_base = pcie->dbi; >> - pp->root_bus_nr = -1; >> + pp->root_bus_nr = 0; > > similar change for pcie-spear13xx.c should be needed as well. > Right, will add this in next version. >> pp->ops = &ls_pcie_host_ops; >> >> ret = dw_pcie_host_init(pp); >> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c >> index 2e9f84f..b3f0ac7 100644 >> --- a/drivers/pci/host/pcie-designware.c >> +++ b/drivers/pci/host/pcie-designware.c > > [...] > >> -#ifdef CONFIG_PCI_MSI >> - dw_pcie_msi_chip.dev = pp->dev; >> - dw_pci.msi_ctrl = &dw_pcie_msi_chip; >> +#ifdef CONFIG_ARM >> + /* >> + * FIXME: we should really be able to use >> + * of_pci_get_host_bridge_resources on arm32 as well, >> + * but the conversion needs some more testing >> + */ >> + if (global_io_offset < SZ_1M && pp->io_size > 0) { >> + pci_ioremap_io(global_io_offset, pp->io_base); >> + global_io_offset += SZ_64K; >> + pci_add_resource_offset(&res, &pp->io, >> + global_io_offset - pp->io_bus_addr); >> + } >> + pci_add_resource_offset(&res, &pp->mem, >> + pp->mem.start - pp->mem_bus_addr); >> + pci_add_resource(&res, &pp->busn); >> +#else >> + ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base); >> + if (ret) >> + return ret; >> +#endif >> + >> + bus = pci_create_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops, >> + pp, &res); >> + if (!bus) >> + return -ENOMEM; >> + >> +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN >> + bus->msi = container_of(&pp->irq_domain, struct msi_controller, domain); >> +#else >> + bus->msi = &dw_pcie_msi_chip; >> #endif >> >> - dw_pci.nr_controllers = 1; >> - dw_pci.private_data = (void **)&pp; >> + pci_scan_child_bus(bus); >> + if (pp->ops->scan_bus) >> + pp->ops->scan_bus(pp); >> >> - pci_common_init_dev(pp->dev, &dw_pci); >> +#ifdef CONFIG_ARM >> + /* support old dtbs that incorrectly describe IRQs */ >> + pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); >> +#endif >> + >> + pci_assign_unassigned_bus_resources(bus); >> + pci_bus_add_devices(bus); > > As James and Lorenzo has suggested, of_pci_get_host_bridge_resources should > work for ARM as well. I would suggest to move that just after cfg > resource parsing and > then to remove following piece of code. > for_each_of_pci_range(&parser, &range) { > ... > } > ret = of_pci_parse_bus_range(np, &pp->busn); > > Then you can have a loop like > > list_for_each_entry(entry, &res, node) { > struct resource *res_temp = entry->res; > if (resource_type(res_temp) == IORESOURCE_IO) { > } else if (resource_type(res_temp) == IORESOURCE_MEM) { > } > } > > where you can fill, xx_size, xx_bus_addr, xx_mod_base etc. I think it will be better to do like this. And Gabriele already shared a patch about this in this series'discussions, I will try to merge his patch in my next version patchset. > You can also remove global_io_offset variable. will use pci_remap_iospace in next version patch. Many thanks for your comments Zhou > > ~Pratyush > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > > . >
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c index 2d57e19..5c8b6ab 100644 --- a/drivers/pci/host/pci-dra7xx.c +++ b/drivers/pci/host/pci-dra7xx.c @@ -280,6 +280,7 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, pp = &dra7xx->pp; pp->dev = dev; + pp->root_bus_nr = 0; pp->ops = &dra7xx_pcie_host_ops; pp->irq = platform_get_irq(pdev, 1); diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index c139237..4b6db6c 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -534,7 +534,7 @@ static int __init exynos_add_pcie_port(struct pcie_port *pp, } } - pp->root_bus_nr = -1; + pp->root_bus_nr = 0; pp->ops = &exynos_pcie_host_ops; ret = dw_pcie_host_init(pp); diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index fdb9536..c4a80c5 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -541,7 +541,7 @@ static int __init imx6_add_pcie_port(struct pcie_port *pp, } } - pp->root_bus_nr = -1; + pp->root_bus_nr = 0; pp->ops = &imx6_pcie_host_ops; ret = dw_pcie_host_init(pp); diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c index 75333b0..df91f5e 100644 --- a/drivers/pci/host/pci-keystone.c +++ b/drivers/pci/host/pci-keystone.c @@ -312,7 +312,7 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie, return ret; } - pp->root_bus_nr = -1; + pp->root_bus_nr = 0; pp->ops = &keystone_pcie_host_ops; ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np); if (ret) { diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index 4a6e62f..5c7a9c4 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -101,7 +101,7 @@ static int ls_add_pcie_port(struct ls_pcie *pcie) pp = &pcie->pp; pp->dev = pcie->dev; pp->dbi_base = pcie->dbi; - pp->root_bus_nr = -1; + pp->root_bus_nr = 0; pp->ops = &ls_pcie_host_ops; ret = dw_pcie_host_init(pp); diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 2e9f84f..b3f0ac7 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -11,6 +11,7 @@ * published by the Free Software Foundation. */ +#include <linux/hardirq.h> #include <linux/irq.h> #include <linux/irqdomain.h> #include <linux/kernel.h> @@ -67,17 +68,10 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C -static struct hw_pci dw_pci; +static struct pci_ops dw_pcie_ops; static unsigned long global_io_offset; -static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) -{ - BUG_ON(!sys->private_data); - - return sys->private_data; -} - int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) { *val = readl(addr); @@ -238,7 +232,7 @@ static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) { int irq, pos0, i; - struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata); + struct pcie_port *pp = desc->dev->bus->sysdata; pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS, order_base_2(no_irqs)); @@ -281,7 +275,7 @@ static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, { int irq, pos; struct msi_msg msg; - struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata); + struct pcie_port *pp = pdev->bus->sysdata; if (desc->msi_attrib.is_msix) return -EINVAL; @@ -310,7 +304,7 @@ static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) { struct irq_data *data = irq_get_irq_data(irq); struct msi_desc *msi = irq_data_get_msi(data); - struct pcie_port *pp = sys_to_pcie(msi->dev->bus->sysdata); + struct pcie_port *pp = msi->dev->bus->sysdata; clear_irq_range(pp, irq, 1, data->hwirq); } @@ -342,13 +336,15 @@ static const struct irq_domain_ops msi_domain_ops = { .map = dw_pcie_msi_map, }; -int dw_pcie_host_init(struct pcie_port *pp) +int __init dw_pcie_host_init(struct pcie_port *pp) { struct device_node *np = pp->dev->of_node; struct platform_device *pdev = to_platform_device(pp->dev); struct of_pci_range range; struct of_pci_range_parser parser; + struct pci_bus *bus; struct resource *cfg_res; + LIST_HEAD(res); u32 val, na, ns; const __be32 *addrp; int i, index, ret; @@ -502,15 +498,49 @@ int dw_pcie_host_init(struct pcie_port *pp) val |= PORT_LOGIC_SPEED_CHANGE; dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); -#ifdef CONFIG_PCI_MSI - dw_pcie_msi_chip.dev = pp->dev; - dw_pci.msi_ctrl = &dw_pcie_msi_chip; +#ifdef CONFIG_ARM + /* + * FIXME: we should really be able to use + * of_pci_get_host_bridge_resources on arm32 as well, + * but the conversion needs some more testing + */ + if (global_io_offset < SZ_1M && pp->io_size > 0) { + pci_ioremap_io(global_io_offset, pp->io_base); + global_io_offset += SZ_64K; + pci_add_resource_offset(&res, &pp->io, + global_io_offset - pp->io_bus_addr); + } + pci_add_resource_offset(&res, &pp->mem, + pp->mem.start - pp->mem_bus_addr); + pci_add_resource(&res, &pp->busn); +#else + ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base); + if (ret) + return ret; +#endif + + bus = pci_create_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops, + pp, &res); + if (!bus) + return -ENOMEM; + +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN + bus->msi = container_of(&pp->irq_domain, struct msi_controller, domain); +#else + bus->msi = &dw_pcie_msi_chip; #endif - dw_pci.nr_controllers = 1; - dw_pci.private_data = (void **)&pp; + pci_scan_child_bus(bus); + if (pp->ops->scan_bus) + pp->ops->scan_bus(pp); - pci_common_init_dev(pp->dev, &dw_pci); +#ifdef CONFIG_ARM + /* support old dtbs that incorrectly describe IRQs */ + pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); +#endif + + pci_assign_unassigned_bus_resources(bus); + pci_bus_add_devices(bus); return 0; } @@ -653,7 +683,7 @@ static int dw_pcie_valid_config(struct pcie_port *pp, static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - struct pcie_port *pp = sys_to_pcie(bus->sysdata); + struct pcie_port *pp = bus->sysdata; int ret; if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { @@ -677,7 +707,7 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - struct pcie_port *pp = sys_to_pcie(bus->sysdata); + struct pcie_port *pp = bus->sysdata; int ret; if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) @@ -701,64 +731,6 @@ static struct pci_ops dw_pcie_ops = { .write = dw_pcie_wr_conf, }; -static int dw_pcie_setup(int nr, struct pci_sys_data *sys) -{ - struct pcie_port *pp; - - pp = sys_to_pcie(sys); - - if (global_io_offset < SZ_1M && pp->io_size > 0) { - sys->io_offset = global_io_offset - pp->io_bus_addr; - pci_ioremap_io(global_io_offset, pp->io_base); - global_io_offset += SZ_64K; - pci_add_resource_offset(&sys->resources, &pp->io, - sys->io_offset); - } - - sys->mem_offset = pp->mem.start - pp->mem_bus_addr; - pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); - pci_add_resource(&sys->resources, &pp->busn); - - return 1; -} - -static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) -{ - struct pci_bus *bus; - struct pcie_port *pp = sys_to_pcie(sys); - - pp->root_bus_nr = sys->busnr; - bus = pci_create_root_bus(pp->dev, sys->busnr, - &dw_pcie_ops, sys, &sys->resources); - if (!bus) - return NULL; - - pci_scan_child_bus(bus); - - if (bus && pp->ops->scan_bus) - pp->ops->scan_bus(pp); - - return bus; -} - -static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); - int irq; - - irq = of_irq_parse_and_map_pci(dev, slot, pin); - if (!irq) - irq = pp->irq; - - return irq; -} - -static struct hw_pci dw_pci = { - .setup = dw_pcie_setup, - .scan = dw_pcie_scan_bus, - .map_irq = dw_pcie_map_irq, -}; - void dw_pcie_setup_rc(struct pcie_port *pp) { u32 val; diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c index 020d788..e78ddf8 100644 --- a/drivers/pci/host/pcie-spear13xx.c +++ b/drivers/pci/host/pcie-spear13xx.c @@ -287,7 +287,7 @@ static int spear13xx_add_pcie_port(struct pcie_port *pp, return ret; } - pp->root_bus_nr = -1; + pp->root_bus_nr = 0; pp->ops = &spear13xx_pcie_host_ops; ret = dw_pcie_host_init(pp);