From patchwork Fri Jun 12 02:49:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "majun (F)" X-Patchwork-Id: 6594011 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 64DAAC0020 for ; Fri, 12 Jun 2015 02:54:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7FAFD2065A for ; Fri, 12 Jun 2015 02:54:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A262E20658 for ; Fri, 12 Jun 2015 02:54:28 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z3F4B-0006XB-EH; Fri, 12 Jun 2015 02:51:35 +0000 Received: from szxga03-in.huawei.com ([119.145.14.66]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z3F42-0006ON-MK for linux-arm-kernel@lists.infradead.org; Fri, 12 Jun 2015 02:51:32 +0000 Received: from 172.24.2.119 (EHLO SZXEML429-HUB.china.huawei.com) ([172.24.2.119]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BHO06749; Fri, 12 Jun 2015 10:50:12 +0800 (CST) Received: from localhost (10.177.236.124) by SZXEML429-HUB.china.huawei.com (10.82.67.184) with Microsoft SMTP Server id 14.3.158.1; Fri, 12 Jun 2015 10:50:04 +0800 From: Ma Jun To: , , , , , , , , , Subject: [PATCH v2 3/3] dt-binding:Documents the mbigen bindings Date: Fri, 12 Jun 2015 10:49:59 +0800 Message-ID: <1434077399-32200-4-git-send-email-majun258@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1434077399-32200-1-git-send-email-majun258@huawei.com> References: <1434077399-32200-1-git-send-email-majun258@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.236.124] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.557A48E5.0003, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 450ae8ed34549ffeaa882d76bb5016cd X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150611_195129_157343_48D3CFE0 X-CRM114-Status: UNSURE ( 9.45 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.3 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the mbigen msi interrupt controller bindings document Signed-off-by: Ma Jun --- Documentation/devicetree/bindings/arm/mbigen.txt | 59 ++++++++++++++++++++++ 1 files changed, 59 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mbigen.txt diff --git a/Documentation/devicetree/bindings/arm/mbigen.txt b/Documentation/devicetree/bindings/arm/mbigen.txt new file mode 100644 index 0000000..c7c261b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mbigen.txt @@ -0,0 +1,59 @@ +Hisilicon mbigen device tree bindings. +======================================= + +Mbigen means: message based interrupt generator. + +MBI is kind of msi interrupt only used on Non-PCI devices. + +To reduce the wired interrupt number connected to GIC, +Hisilicon designed mbigen to collect and generate interrupt. + + +Non-pci devices can connect to mbigen and gnerate the inteerrupt +by wirtting ITS register. + +The mbigen and devices connect to mbigen have the following properties: + + +Mbigen required properties: +------------------------------------------- +-compatible: Should be "hisilicon,mbi-gen" +-msi-parent: should specified the ITS mbigen connected +-interrupt controller: Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value is 2 for now. + + The 1st cell is the interrupt number(Hwirq).This value depends on + the Soc design. + + The 2nd cell is the interrupt trigger type, encoded as follows: + 1 = edge triggered + 4 = level triggered + +- reg: Specifies the base physical address and size of the ITS + registers. + +Examples: + + mbigen_pa: interrupt-controller@4c030000 { + compatible = "hisilicon,mbi-gen"; + msi-parent = <&its_pa>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4c030000 0x10000>; + }; + +Device connect to mbigen required properties: +---------------------------------------------------- +-interrupt-parent: Specifies the mbigen node which device connected. +-interrupts:specifies the interrupt source.The first cell is hwirq num, the + second number is trigger type. + +Examples: + usb0: ehci@a1000000 { + compatible = "generic-ehci"; + interrupt-parent = <&mbigen_pa>; + reg = <0xa1000000 0x10000>; + interrupts = <20 4>; + }; +