From patchwork Thu Jun 25 14:31:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vitaly Andrianov X-Patchwork-Id: 6675641 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 41FA7C05AC for ; Thu, 25 Jun 2015 14:31:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 55BBD206C0 for ; Thu, 25 Jun 2015 14:31:16 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5C4C1206CB for ; Thu, 25 Jun 2015 14:31:15 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z889R-0000cA-MA; Thu, 25 Jun 2015 14:29:13 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z888c-0007gs-Kd for linux-arm-kernel@lists.infradead.org; Thu, 25 Jun 2015 14:28:24 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id t5PERZOP027427; Thu, 25 Jun 2015 09:27:35 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t5PERZNH024300; Thu, 25 Jun 2015 09:27:35 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Thu, 25 Jun 2015 09:27:35 -0500 Received: from uda0794637.am.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t5PERWDZ007688; Thu, 25 Jun 2015 09:27:34 -0500 From: Vitaly Andrianov To: , , , , , , , , , Subject: [PATCH v2 2/3] ARM: keystone: ecc: add ARM L1/L2 ecc interrupt handling Date: Thu, 25 Jun 2015 10:31:49 -0400 Message-ID: <1435242710-31346-3-git-send-email-vitalya@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1435242710-31346-1-git-send-email-vitalya@ti.com> References: <1435242710-31346-1-git-send-email-vitalya@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150625_072822_958524_8E48342E X-CRM114-Status: GOOD ( 15.03 ) X-Spam-Score: -8.3 (--------) Cc: Murali Karicheri , Vitaly Andrianov , Hao Zhang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds ARM L1/L2 ECC handler support interrupt handling for Keystone II devices, the kernel will reboot if the error is 2-bit error for L1/L2 ECC error. Signed-off-by: Hao Zhang Signed-off-by: Murali Karicheri Signed-off-by: Vitaly Andrianov --- arch/arm/mach-keystone/keystone.c | 69 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c index 4534c7d..0b28fca 100644 --- a/arch/arm/mach-keystone/keystone.c +++ b/arch/arm/mach-keystone/keystone.c @@ -9,9 +9,12 @@ * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. */ +#include #include #include +#include #include +#include #include #include @@ -46,6 +49,72 @@ static int keystone_platform_notifier(struct notifier_block *nb, return NOTIFY_OK; } +#define L2_INTERN_ASYNC_ERROR BIT(30) +#define AXI_ASYNC_ERROR BIT(29) + +static void check_ecc_error(void) +{ + u32 status, fault; + + /* read and clear L2ECTLR CP15 register for L2 ECC error */ + asm("mrc p15, 1, %0, c9, c0, 3" : "=r"(status)); + + if (status & L2_INTERN_ASYNC_ERROR) { + status &= ~L2_INTERN_ASYNC_ERROR; + asm("mcr p15, 1, %0, c9, c0, 3" : : "r" (status)); + asm("mcr p15, 0, %0, c5, c1, 0" : "=r" (fault)); + /* + * Do a machine restart as this is double bit ECC error + * that can't be corrected + */ + pr_err("ARM Cortex A15 L1/L2 ECC error, CP15 ADFSR 0x%x\n", + fault); + machine_restart(NULL); + /* we should never cone here*/ + } + + if (status & AXI_ASYNC_ERROR) + pr_err("ARM Cortex A15 AXI async error shouldn't cause an nterrupt\n"); +} + +static irqreturn_t arm_l1l2_ecc_err_irq_handler(int irq, void *reg_virt) +{ + check_ecc_error(); + + return IRQ_HANDLED; +} + +static int __init keystone_init_misc(void) +{ + struct device_node *node = NULL; + int error_irq = 0; + int ret; + + /* + * check if we already have ecc error. Reboot if it is double bit + * error. + */ + check_ecc_error(); + + /* add ARM ECC L1/L2 cache error handler */ + node = of_find_compatible_node(NULL, NULL, "ti,keystone-sys"); + if (node) + error_irq = irq_of_parse_and_map(node, 0); + + if (!error_irq) { + pr_warn("Warning!! arm L1/L2 ECC irq number not defined\n"); + return 0; + } + + if (request_irq(error_irq, arm_l1l2_ecc_err_irq_handler, 0, + "a15-l1l2-ecc-err-irq", 0) < 0) { + WARN_ON("request_irq fail for arm L1/L2 ECC error irq\n"); + } + + return ret; +} +subsys_initcall(keystone_init_misc); + static void __init keystone_init(void) { keystone_pm_runtime_init();