Message ID | 1435338654-9098-1-git-send-email-fabio.estevam@freescale.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP |
On Fri, Jun 26, 2015 at 02:10:53PM -0300, Fabio Estevam wrote: > Currently it is not possible to have HDMI and LVDS working simultaneously, > because both ports try to use PLL5. > > Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be > driven from independent sources. > > With this change the LDB pixel clock goes to 68.57 MHz, which is still > within the valid range for the HSD100PXN1 LVDS panel. > > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> > Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Applied both, thanks.
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index a626e6d..cca847e 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -141,6 +141,13 @@ status = "okay"; }; +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio4 9 0>;