From patchwork Fri Jun 26 18:52:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timur Tabi X-Patchwork-Id: 6682691 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BA9D29F380 for ; Fri, 26 Jun 2015 18:55:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C3F6B2063B for ; Fri, 26 Jun 2015 18:55:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A97D820625 for ; Fri, 26 Jun 2015 18:55:33 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z8Ykk-0000S7-Kk; Fri, 26 Jun 2015 18:53:30 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z8YkH-0000Kk-O2 for linux-arm-kernel@lists.infradead.org; Fri, 26 Jun 2015 18:53:03 +0000 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 438BA140D4D; Fri, 26 Jun 2015 18:52:41 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 322CD140D53; Fri, 26 Jun 2015 18:52:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from timur-ubuntu.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com [67.52.129.61]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: timur@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E9C60140D4D; Fri, 26 Jun 2015 18:52:39 +0000 (UTC) From: Timur Tabi To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Shanker Donthineni , awallis@codeaurora.org, abhimany@codeaurora.org, will.deacon@arm.com, sboyd@codeaurora.org, Vipul Gandhi Subject: [PATCH 3/3] [v2] ARM64: TTY: hvc_dcc: Add support for ARM64 dcc Date: Fri, 26 Jun 2015 13:52:36 -0500 Message-Id: <1435344756-20901-3-git-send-email-timur@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1435344756-20901-1-git-send-email-timur@codeaurora.org> References: <1435344756-20901-1-git-send-email-timur@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150626_115301_922267_F07934D6 X-CRM114-Status: GOOD ( 21.43 ) X-Spam-Score: -3.3 (---) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Abhimanyu Kapur Add support for debug communications channel based hvc console for arm64 cpus. Signed-off-by: Abhimanyu Kapur Signed-off-by: Timur Tabi --- arch/arm64/include/asm/dcc.h | 52 ++++++++++++++++++++++++++++++++++++++++++++ drivers/tty/hvc/Kconfig | 2 +- drivers/tty/hvc/hvc_dcc.c | 11 ++++++++++ 3 files changed, 64 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/include/asm/dcc.h diff --git a/arch/arm64/include/asm/dcc.h b/arch/arm64/include/asm/dcc.h new file mode 100644 index 0000000..d550173 --- /dev/null +++ b/arch/arm64/include/asm/dcc.h @@ -0,0 +1,52 @@ +/* Copyright (c) 2014 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * A call to __dcc_getchar() or __dcc_putchar() is typically followed by + * a call to __dcc_getstatus(). We want to make sure that the CPU does + * not speculative read the DCC status before executing the read or write + * instruction. That's what the ISBs are for. + * + * The 'volatile' ensures that the compiler does not cache the status bits, + * and instead reads the DCC register every time. + */ +#ifndef __ASM_DCC_H +#define __ASM_DCC_H + +#include + +static inline u32 __dcc_getstatus(void) +{ + u32 ret; + + asm volatile("mrs %0, mdccsr_el0" : "=r" (ret)); + + return ret; +} + +static inline char __dcc_getchar(void) +{ + char c; + + asm volatile("mrs %0, dbgdtrrx_el0" : "=r" (c)); + isb(); + + return c; +} + +static inline void __dcc_putchar(char c) +{ + asm volatile("msr dbgdtrtx_el0, %0" + : /* No output register */ + : "r" (c)); + isb(); +} + +#endif diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig index 2c6883c..9a60d18 100644 --- a/drivers/tty/hvc/Kconfig +++ b/drivers/tty/hvc/Kconfig @@ -88,7 +88,7 @@ config HVC_UDBG config HVC_DCC bool "ARM JTAG DCC console" - depends on ARM + depends on ARM || ARM64 select HVC_DRIVER help This console uses the JTAG DCC on ARM to create a console under the HVC diff --git a/drivers/tty/hvc/hvc_dcc.c b/drivers/tty/hvc/hvc_dcc.c index f8b8cf2..d4c7073 100644 --- a/drivers/tty/hvc/hvc_dcc.c +++ b/drivers/tty/hvc/hvc_dcc.c @@ -226,11 +226,22 @@ static const struct hv_ops hvc_dcc_get_put_ops = { static int __init hvc_dcc_console_init(void) { int ret; +#ifdef CONFIG_ARM64 + u32 val; +#endif /* This always runs on boot core */ if (!hvc_dcc_check()) return -ENODEV; +#ifdef CONFIG_ARM64 + /* Disable user-space access to DCC */ + asm("msr mdscr_el1, %0 " + "orr %0, %0, #4096 " /* TDCC */ + "msr %0, mdscr_el1 " + : "=r" (val)); +#endif + /* Returns -1 if error */ ret = hvc_instantiate(0, 0, &hvc_dcc_get_put_ops);