From patchwork Wed Jul 1 09:13:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Courbot X-Patchwork-Id: 6701591 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 86E319F1C1 for ; Wed, 1 Jul 2015 09:16:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 560B520685 for ; Wed, 1 Jul 2015 09:16:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7369220658 for ; Wed, 1 Jul 2015 09:16:28 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZAE6D-00045J-TU; Wed, 01 Jul 2015 09:14:33 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZAE66-0003yI-JV for linux-arm-kernel@lists.infradead.org; Wed, 01 Jul 2015 09:14:27 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Wed, 01 Jul 2015 02:14:35 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Wed, 01 Jul 2015 02:13:52 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 01 Jul 2015 02:13:52 -0700 Received: from percival.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.342.0; Wed, 1 Jul 2015 02:14:07 -0700 From: Alexandre Courbot To: Thierry Reding , Stephen Warren Subject: [PATCH 2/4] ARM: tegra: venice2: Add GK20A GPU DT node Date: Wed, 1 Jul 2015 18:13:46 +0900 Message-ID: <1435742028-8237-3-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 2.4.4 In-Reply-To: <1435742028-8237-1-git-send-email-acourbot@nvidia.com> References: <1435742028-8237-1-git-send-email-acourbot@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150701_021426_685137_15E456EC X-CRM114-Status: GOOD ( 11.81 ) X-Spam-Score: -7.5 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gnurou@gmail.com, linux-kernel@vger.kernel.org, Alexandre Courbot , linux-tegra@vger.kernel.org, Thierry Reding , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding Add the device-tree node for the GK20A GPU and leave it disabled. It is the responsability of the bootloader to enable it if the VPR registers have been programmed such as the GPU can operate. Signed-off-by: Thierry Reding Signed-off-by: Alexandre Courbot --- arch/arm/boot/dts/tegra124-venice2.dts | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 5c3f7813360d..497a50ebfe44 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -43,6 +43,14 @@ }; }; + gpu@0,57000000 { + /* + * Node left disabled on purpose - the bootloader will enable + * it after having set the VPR up + */ + vdd-supply = <&vdd_gpu>; + }; + pinmux: pinmux@0,70000868 { pinctrl-names = "boot"; pinctrl-0 = <&pinmux_boot>; @@ -735,7 +743,7 @@ regulator-always-on; }; - sd6 { + vdd_gpu: sd6 { regulator-name = "+VDD_GPU_AP"; regulator-min-microvolt = <650000>; regulator-max-microvolt = <1200000>;