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Wed, 01 Jul 2015 22:21:18 +0900 (KST) From: Chanwoo Choi To: s.nawrocki@samsung.com, tomasz.figa@gmail.com, mturquette@baylibre.com, sboyd@codeaurora.org, kgene@kernel.org, k.kozlowski@samsung.com Subject: [PATCH v5 1/3] clk: samsung: exynos3250: Add cpu clock configuration data and instaniate cpu clock Date: Wed, 01 Jul 2015 22:21:15 +0900 Message-id: <1435756877-26736-2-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.5.5 In-reply-to: <1435756877-26736-1-git-send-email-cw00.choi@samsung.com> References: <1435756877-26736-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupikeLIzCtJLcpLzFFi42JZI2JSoOv/cnKowZcV7BYbZ6xntbj+5Tmr xfwj51gtXr8wtOh//JrZ4mzTG3aLTY+vsVp87LnHanF51xw2ixnn9zFZXDzlanH4TTurxY8z 3SwWHcsYLVbt+sPowO/x/kYru8flvl4mj52z7rJ7bFrVyeaxeUm9R9+WVYwenzfJBbBHcdmk pOZklqUW6dslcGU0n9rFXtAsW3G6czpTA+Nl8S5GTg4JAROJKz8eMkPYYhIX7q1nA7GFBJYy Slw45w5T86R5ETNEfDqjxN0PwV2MXED2F0aJfcfngzWwCWhJ7H9xgw0kISLQyyjx/1ozI4jD LNDJJLH+wz1GkCphgVyJE/0HwTpYBFQl2n++AIvzCrhKbG5tYIRYpyCxbPlMVhCbU8BNYldH IzvEaleJGRdamUGGSgjcYpfYu/4QK8QgAYlvkw+xdDFyACVkJTYdgHpHUuLgihssExiFFzAy rGIUTS1ILihOSi8y1CtOzC0uzUvXS87P3cQIjKLT/5717mC8fcD6EKMAB6MSD6+A2ORQIdbE suLK3EOMpkAbJjJLiSbnA2M1ryTe0NjMyMLUxNTYyNzSTEmcV1HqZ7CQQHpiSWp2ampBalF8 UWlOavEhRiYOTqkGxolTLWapHOQoYeZrlH1p16U5edUx+T/7uBgUWw++KzxXmnHzRcdizcNz YqZdK71y8XfLh13Bfz99FXSPUelJO/MzluHvMenjRxSiNKZLL5lz+742e8i3wztMDY63xARb zHO4LNmnk9X8YFVwfeQ2EY/L0rvirVc8VKitNlpz9er7NfvdMhyFmpVYijMSDbWYi4oTASL7 9lSdAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCIsWRmVeSWpSXmKPExsVy+t9jQV3/l5NDDZrrLDbOWM9qcf3Lc1aL +UfOsVq8fmFo0f/4NbPF2aY37BabHl9jtfjYc4/V4vKuOWwWM87vY7K4eMrV4vCbdlaLH2e6 WSw6ljFarNr1h9GB3+P9jVZ2j8t9vUweO2fdZffYtKqTzWPzknqPvi2rGD0+b5ILYI9qYLTJ SE1MSS1SSM1Lzk/JzEu3VfIOjneONzUzMNQ1tLQwV1LIS8xNtVVy8QnQdcvMATpaSaEsMacU KBSQWFyspG+HaUJoiJuuBUxjhK5vSBBcj5EBGkhYw5jRfGoXe0GzbMXpzulMDYyXxbsYOTkk BEwknjQvYoawxSQu3FvPBmILCUxnlLj7IbiLkQvI/sIose/4fLAEm4CWxP4XN9hAEiICvYwS /681M4I4zAKdTBLrP9xjBKkSFsiVONF/EKyDRUBVov3nC7A4r4CrxObWBkaIdQoSy5bPZAWx OQXcJHZ1NLJDrHaVmHGhlXkCI+8CRoZVjKKpBckFxUnpuYZ6xYm5xaV56XrJ+bmbGMEx+kxq B+PKBotDjAIcjEo8vAJik0OFWBPLiitzDzFKcDArifB+mQoU4k1JrKxKLcqPLyrNSS0+xGgK dNVEZinR5Hxg+sgriTc0NjEzsjQyN7QwMjZXEuc9me8TKiSQnliSmp2aWpBaBNPHxMEp1cDI YOYdcSr+wsWuix4aV9I5nv5eVBHgmBDwtjvuTUcRx8tVNYn6IYuuGAv9PplyOur+1C7b93vS 5Xp/96iYnumK95z4aoPEtysTdry/fOal66lLqk8KueY9OaX89Fez076PU1RKnk2V82ZNO36i nk3MJFr0Q24g2y7+D0FXVlwWPhC3P2jGZ10FJZbijERDLeai4kQA+C/vd+cCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150701_062143_250064_C437799E X-CRM114-Status: GOOD ( 13.14 ) X-Spam-Score: -7.5 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, b.zolnierkie@samsung.com, linux-kernel@vger.kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, thomas.ab@samsung.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch add CPU clock configuration data and instantiate the CPU clock type for Exynos3250 to support Samsung specific cpu-clock type. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi Acked-by: Kyungmin Park Reviewed-by: Krzysztof Kozlowski Acked-by: Stephen Boyd --- drivers/clk/samsung/clk-exynos3250.c | 32 ++++++++++++++++++++++++++++++-- include/dt-bindings/clock/exynos3250.h | 1 + 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index 538de66a759e..378ad5ad3492 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -19,6 +19,7 @@ #include #include "clk.h" +#include "clk-cpu.h" #include "clk-pll.h" #define SRC_LEFTBUS 0x4200 @@ -319,8 +320,10 @@ static struct samsung_mux_clock mux_clks[] __initdata = { MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p, SRC_CPU, 24, 1), MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1), - MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1), - MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), + MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1, + CLK_SET_RATE_PARENT, 0), + MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + CLK_SET_RATE_PARENT, 0), }; static struct samsung_div_clock div_clks[] __initdata = { @@ -772,6 +775,26 @@ static struct samsung_cmu_info cmu_info __initdata = { .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs), }; +#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \ + (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ + ((corem) << 4)) +#define E3250_CPU_DIV1(hpm, copy) \ + (((hpm) << 4) | ((copy) << 0)) + +static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = { + { 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), }, + { 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), }, + { 0 }, +}; + static void __init exynos3250_cmu_init(struct device_node *np) { struct samsung_clk_provider *ctx; @@ -780,6 +803,11 @@ static void __init exynos3250_cmu_init(struct device_node *np) if (!ctx) return; + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_core_p[0], mout_core_p[1], 0x14200, + e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d), + CLK_CPU_HAS_DIV1); + exynos3_core_down_clock(ctx->reg_base); } CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init); diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index aab088d30199..63d01c15d2b3 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -31,6 +31,7 @@ #define CLK_FOUT_VPLL 4 #define CLK_FOUT_UPLL 5 #define CLK_FOUT_MPLL 6 +#define CLK_ARM_CLK 7 /* Muxes */ #define CLK_MOUT_MPLL_USER_L 16