From patchwork Thu Jul 2 00:42:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 6707191 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EA132C05AC for ; Thu, 2 Jul 2015 00:45:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1D06B203A1 for ; Thu, 2 Jul 2015 00:45:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2E5EC203A0 for ; Thu, 2 Jul 2015 00:45:54 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZASb3-0007lC-M6; Thu, 02 Jul 2015 00:43:21 +0000 Received: from mailout3.samsung.com ([203.254.224.33]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZASas-0007Mg-N1 for linux-arm-kernel@lists.infradead.org; Thu, 02 Jul 2015 00:43:11 +0000 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NQU02W3A4N6A4B0@mailout3.samsung.com> for linux-arm-kernel@lists.infradead.org; Thu, 02 Jul 2015 09:42:42 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.116]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 9B.A8.29324.20984955; Thu, 2 Jul 2015 09:42:42 +0900 (KST) X-AuditID: cbfee68d-f79106d00000728c-e0-5594890230c2 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 19.BE.25346.20984955; Thu, 2 Jul 2015 09:42:42 +0900 (KST) Received: from chan.10.32.193.11 ([10.252.81.195]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NQU0053G4N6Z0B0@mmp1.samsung.com>; Thu, 02 Jul 2015 09:42:42 +0900 (KST) From: Chanwoo Choi To: s.nawrocki@samsung.com, tomasz.figa@gmail.com, mturquette@baylibre.com, sboyd@codeaurora.org, kgene@kernel.org, k.kozlowski@samsung.com Subject: [PATCH v6 1/3] clk: samsung: exynos3250: Add cpu clock configuration data and instaniate cpu clock Date: Thu, 02 Jul 2015 09:42:39 +0900 Message-id: <1435797761-3339-2-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.5.5 In-reply-to: <1435797761-3339-1-git-send-email-cw00.choi@samsung.com> References: <1435797761-3339-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupmkeLIzCtJLcpLzFFi42JZI2JSosvUOSXUoO20pcXGGetZLa5/ec5q Mf/IOVaL1y8MLfofv2a2ONv0ht1i0+NrrBYfe+6xWlzeNYfNYsb5fUwWF0+5Whx+085q8eNM N4tFxzJGi1W7/jA68Hu8v9HK7nG5r5fJY+esu+wem1Z1snlsXlLv0bdlFaPH501yAexRXDYp qTmZZalF+nYJXBldW3tYC/bLVtyefIC1gbFLoouRk0NCwERiVuMNdghbTOLCvfVsILaQwFJG id9Ti2Bq7p4+xtLFyAUUX8QosWHzSmYI5wujxNaOTrBuNgEtif0vbrCBJEQEehkl/l9rZgRx mAU6mSTWf7jHCFIlLJArseTBWzCbRUBV4snmR2DdvAIuEn3bZ0HdoSCxbPlMVhCbU8BV4vKP jSwQN7lITJz1EOwOCYF77BLbFv5ghhgkIPFt8iGgBAdQQlZi0wFmiDmSEgdX3GCZwCi8gJFh FaNoakFyQXFSepGhXnFibnFpXrpecn7uJkZgHJ3+96x3B+PtA9aHGAU4GJV4eAOqpoQKsSaW FVfmHmI0BdowkVlKNDkfGK15JfGGxmZGFqYmpsZG5pZmSuK8ilI/g4UE0hNLUrNTUwtSi+KL SnNSiw8xMnFwSjUwHmla01DhnficoeZfvs41adUVM7+nW28pdN7P+OnN8WOKTK9nz953jOG6 R0NtASfnjdUp56LNZy3nvLSha8KUJp82wVgWkyjPovd7fTYvzpmfsdLiAeOq/ia5G3s1ghlW 9nrmmbHkmUWy1lfYfZ5/O2+PeW/Xq4+hl1odJ80467ux6cKvKRarlViKMxINtZiLihMBR9lK 4p4CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGIsWRmVeSWpSXmKPExsVy+t9jAV2mzimhBlcfGFhsnLGe1eL6l+es FvOPnGO1eP3C0KL/8Wtmi7NNb9gtNj2+xmrxseceq8XlXXPYLGac38dkcfGUq8XhN+2sFj/O dLNYdCxjtFi16w+jA7/H+xut7B6X+3qZPHbOusvusWlVJ5vH5iX1Hn1bVjF6fN4kF8Ae1cBo k5GamJJapJCal5yfkpmXbqvkHRzvHG9qZmCoa2hpYa6kkJeYm2qr5OIToOuWmQN0tZJCWWJO KVAoILG4WEnfDtOE0BA3XQuYxghd35AguB4jAzSQsIYxo2trD2vBftmK25MPsDYwdkl0MXJy SAiYSNw9fYwFwhaTuHBvPVsXIxeHkMAiRokNm1cyQzhfGCW2dnSyg1SxCWhJ7H9xA6xKRKCX UeL/tWZGEIdZoJNJYv2He4wgVcICuRJLHrwFs1kEVCWebH4E1s0r4CLRt30WO8Q+BYlly2ey gticAq4Sl39sBLtDCKhm4qyHLBMYeRcwMqxiFE0tSC4oTkrPNdQrTswtLs1L10vOz93ECI7T Z1I7GFc2WBxiFOBgVOLhXVEzJVSINbGsuDL3EKMEB7OSCO+VIKAQb0piZVVqUX58UWlOavEh RlOgqyYyS4km5wNTSF5JvKGxiZmRpZG5oYWRsbmSOO/JfJ9QIYH0xJLU7NTUgtQimD4mDk6p Bkb3g2638rO77Ev9dXm9Vze+1jO++uP2i+Pn13JKTvLk+T/544GN+psuuedtrNjwOT7eVvtb u1x/a7Hxs4BKkauN95Ntfy7kkv3yqe6NhnwMr+yVa1fK3BeEf9IXPJq+7N/6rJzpLae2zv58 fa0km/221E8J3/P67aKmL2Ry6cuqvBCnq7WlNECJpTgj0VCLuag4EQAbf3BE6QIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150701_174310_928471_7B3E477F X-CRM114-Status: GOOD ( 12.92 ) X-Spam-Score: -7.5 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, b.zolnierkie@samsung.com, linux-kernel@vger.kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, thomas.ab@samsung.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch add CPU clock configuration data and instantiate the CPU clock type for Exynos3250 to support Samsung specific cpu-clock type. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi Acked-by: Kyungmin Park Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos3250.c | 32 ++++++++++++++++++++++++++++++-- include/dt-bindings/clock/exynos3250.h | 1 + 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index 538de66a759e..378ad5ad3492 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -19,6 +19,7 @@ #include #include "clk.h" +#include "clk-cpu.h" #include "clk-pll.h" #define SRC_LEFTBUS 0x4200 @@ -319,8 +320,10 @@ static struct samsung_mux_clock mux_clks[] __initdata = { MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p, SRC_CPU, 24, 1), MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1), - MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1), - MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), + MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1, + CLK_SET_RATE_PARENT, 0), + MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + CLK_SET_RATE_PARENT, 0), }; static struct samsung_div_clock div_clks[] __initdata = { @@ -772,6 +775,26 @@ static struct samsung_cmu_info cmu_info __initdata = { .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs), }; +#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \ + (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ + ((corem) << 4)) +#define E3250_CPU_DIV1(hpm, copy) \ + (((hpm) << 4) | ((copy) << 0)) + +static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = { + { 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), }, + { 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), }, + { 0 }, +}; + static void __init exynos3250_cmu_init(struct device_node *np) { struct samsung_clk_provider *ctx; @@ -780,6 +803,11 @@ static void __init exynos3250_cmu_init(struct device_node *np) if (!ctx) return; + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_core_p[0], mout_core_p[1], 0x14200, + e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d), + CLK_CPU_HAS_DIV1); + exynos3_core_down_clock(ctx->reg_base); } CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init); diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index aab088d30199..63d01c15d2b3 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -31,6 +31,7 @@ #define CLK_FOUT_VPLL 4 #define CLK_FOUT_UPLL 5 #define CLK_FOUT_MPLL 6 +#define CLK_ARM_CLK 7 /* Muxes */ #define CLK_MOUT_MPLL_USER_L 16