From patchwork Mon Jul 13 12:39:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 6779031 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C60019F2E8 for ; Mon, 13 Jul 2015 12:43:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DA7862055A for ; Mon, 13 Jul 2015 12:43:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EC4A220528 for ; Mon, 13 Jul 2015 12:43:54 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZEd3b-0007kp-AD; Mon, 13 Jul 2015 12:42:03 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZEd2h-0006Bg-Nn for linux-arm-kernel@lists.infradead.org; Mon, 13 Jul 2015 12:41:08 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 13 Jul 2015 05:41:21 -0700 Received: from hqemhub02.nvidia.com ([172.20.150.31]) by hqnvupgp08.nvidia.com (PGP Universal service); Mon, 13 Jul 2015 05:40:50 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Mon, 13 Jul 2015 05:40:50 -0700 Received: from jonathanh-lm.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.342.0; Mon, 13 Jul 2015 05:40:50 -0700 From: Jon Hunter To: Stephen Warren , Thierry Reding , Alexandre Courbot , Philipp Zabel , Peter De Schrijver , Prashant Gaikwad , =?UTF-8?q?Terje=20Bergstr=C3=B6m?= , Hans de Goede , Tejun Heo Subject: [PATCH V3 09/19] soc: tegra: pmc: Prepare for migrating to generic PM domains Date: Mon, 13 Jul 2015 13:39:47 +0100 Message-ID: <1436791197-32358-10-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1436791197-32358-1-git-send-email-jonathanh@nvidia.com> References: <1436791197-32358-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150713_054107_811421_A0B69CD3 X-CRM114-Status: GOOD ( 15.74 ) X-Spam-Score: -8.3 (--------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Ulf Hansson , Vince Hsu , Kevin Hilman , linux-pm@vger.kernel.org, "Rafael J. Wysocki" , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When turning on and off power-domains it is necessary to enable specific clocks in order to de-assert/assert various reset signals to place the logic into a good state. Currently, clocks required for turning on a power-domain are left enabled by the PMC driver because these clocks are also needed by the IP blocks to operated. When migrating to the generic PM domain infrastructure, control of the powergates is abstracted from the drivers and therefore, it is desirable to disabled the clocks after turning on the power-domain and let the drivers enable the clocks it needs later. However, because this behaviour is different it is necessary to add a new API that drivers can use whether generic PM domains are used or not so that the behaviour is the same. Hence, add a new API that disables the clocks after turning on the power domain. Similarly, for disabling a power-domain add a new API to abstract the management of the clocks so that drivers can be migrated to generic PM domains. Signed-off-by: Jon Hunter --- drivers/soc/tegra/pmc.c | 23 +++++++++++++++++++++++ include/soc/tegra/pmc.h | 30 ++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 180d434deec5..934653785bb7 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -331,6 +331,29 @@ err_power: } EXPORT_SYMBOL(tegra_powergate_sequence_power_up); +int tegra_powergate_power_off_legacy(int id, struct clk *clk, + struct reset_control *rst) +{ + int ret; + + ret = clk_prepare_enable(clk); + if (ret) + return ret; + + usleep_range(10, 20); + + reset_control_assert(rst); + + usleep_range(10, 20); + + clk_disable_unprepare(clk); + + usleep_range(10, 20); + + return tegra_powergate_power_off(id); +} +EXPORT_SYMBOL(tegra_powergate_power_off_legacy); + #ifdef CONFIG_SMP /** * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h index 3a014c121399..4ca91d39304d 100644 --- a/include/soc/tegra/pmc.h +++ b/include/soc/tegra/pmc.h @@ -19,6 +19,8 @@ #ifndef __SOC_TEGRA_PMC_H__ #define __SOC_TEGRA_PMC_H__ +#include +#include #include #include @@ -117,6 +119,22 @@ int tegra_powergate_remove_clamping(int id); int tegra_powergate_sequence_power_up(int id, struct clk *clk, struct reset_control *rst); +static inline int tegra_powergate_power_on_legacy(int id, struct clk *clk, + struct reset_control *rst) +{ + int err = tegra_powergate_sequence_power_up(id, clk, rst); + + if (!err) { + usleep_range(10, 20); + clk_disable_unprepare(clk); + } + + return err; +} + +int tegra_powergate_power_off_legacy(int id, struct clk *clk, + struct reset_control *rst); + int tegra_io_rail_power_on(int id); int tegra_io_rail_power_off(int id); #else @@ -155,6 +173,18 @@ static inline int tegra_io_rail_power_off(int id) { return -ENOSYS; } + +static inline int tegra_powergate_power_on_legacy(int id, struct clk *clk, + struct reset_control *rst) +{ + return -ENOTSUPP; +} + +static inline int tegra_powergate_power_off_legacy(int id, struct clk *clk, + struct reset_control *rst) +{ + return -ENOTSUPP; +} #endif /* CONFIG_ARCH_TEGRA */ #endif /* __SOC_TEGRA_PMC_H__ */