From patchwork Mon Jul 13 12:39:51 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 6779071 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E251AC05AC for ; Mon, 13 Jul 2015 12:44:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DBD222051C for ; Mon, 13 Jul 2015 12:44:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DA23320528 for ; Mon, 13 Jul 2015 12:44:36 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZEd4H-0000gU-Ul; Mon, 13 Jul 2015 12:42:45 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZEd2z-0006KY-Rr for linux-arm-kernel@lists.infradead.org; Mon, 13 Jul 2015 12:41:26 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 13 Jul 2015 05:40:54 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Mon, 13 Jul 2015 05:41:05 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Mon, 13 Jul 2015 05:41:05 -0700 Received: from jonathanh-lm.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.342.0; Mon, 13 Jul 2015 05:41:05 -0700 From: Jon Hunter To: Stephen Warren , Thierry Reding , Alexandre Courbot , Philipp Zabel , Peter De Schrijver , Prashant Gaikwad , =?UTF-8?q?Terje=20Bergstr=C3=B6m?= , Hans de Goede , Tejun Heo Subject: [PATCH V3 13/19] drm/tegra: gr3d: Add support for generic PM domains Date: Mon, 13 Jul 2015 13:39:51 +0100 Message-ID: <1436791197-32358-14-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1436791197-32358-1-git-send-email-jonathanh@nvidia.com> References: <1436791197-32358-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150713_054125_933436_93D9DABC X-CRM114-Status: GOOD ( 21.13 ) X-Spam-Score: -8.3 (--------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Ulf Hansson , Vince Hsu , Kevin Hilman , linux-pm@vger.kernel.org, "Rafael J. Wysocki" , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support to the tegra gr3d driver for generic PM domains. However, to ensure backward compatibility with older device tree blobs ensure that the driver can work with or without generic PM domains. In order to migrate to generic PM domain infrastructure the necessary changes are: 1. If the "power-domains" property is present in the DT device node then generic PM domains is supported and pm_runtime_enable() should be called for the device. Furthermore, the enabling and disabling of the power-domain is handled via calling pm_runtime_get/put, respectively. 2. To ensure that clocks are managed consistently when generic PM domains are used and are not used, drivers should be migrated to use the tegra_powergate_power_on_legacy() and tegra_powergate_power_off_legacy() functions instead of the current tegra_powergate_sequence_power_up() and tegra_powergate_power_off(). The purpose of the tegra_powergate_power_on_legacy() and tegra_powergate_power_off_legacy() APIs is to mimick the behaviour of the tegra generic power-domain code, such that if generic power domains are not supported the functionality is the same. 3. The main difference between the tegra_powergate_sequence_power_up() API and the tegra_powergate_power_on_legacy() is that the clock used to enable the powergate is not kept enabled when using the tegra_powergate_power_on_legacy() API. Therefore, drivers must enable the clocks they need after calling tegra_powergate_power_on_legacy() and disable these clocks before calling tegra_powergate_power_off_legacy(). Helper functions have been added to the gr3d driver for handling power on and off the power-domains with and without generic PM domain support. Signed-off-by: Jon Hunter --- drivers/gpu/drm/tegra/gr3d.c | 57 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 50 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c index 0b3f2b977ba0..43a9d50e7e44 100644 --- a/drivers/gpu/drm/tegra/gr3d.c +++ b/drivers/gpu/drm/tegra/gr3d.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -238,6 +239,32 @@ static const u32 gr3d_addr_regs[] = { GR3D_GLOBAL_SAMP23SURFADDR(15), }; +static int gr3d_powergate_on(struct platform_device *pdev, int powergate_id, + struct clk *clk, struct reset_control *rst) +{ + int err; + + if (pm_runtime_enabled(&pdev->dev)) + err = pm_runtime_get_sync(&pdev->dev); + else + err = tegra_powergate_power_on_legacy(powergate_id, + clk, rst); + return err; +} + +static int gr3d_powergate_off(struct platform_device *pdev, int powergate_id, + struct clk *clk, struct reset_control *rst) +{ + int err; + + if (pm_runtime_enabled(&pdev->dev)) + err = pm_runtime_put_sync(&pdev->dev); + else + err = tegra_powergate_power_off_legacy(powergate_id, + clk, rst); + return err; +} + static int gr3d_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -281,22 +308,37 @@ static int gr3d_probe(struct platform_device *pdev) } } - err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk, - gr3d->rst); + if (of_property_read_bool(pdev->dev.of_node, "power-domains")) + pm_runtime_enable(&pdev->dev); + + err = gr3d_powergate_on(pdev, TEGRA_POWERGATE_3D, gr3d->clk, gr3d->rst); if (err < 0) { dev_err(&pdev->dev, "failed to power up 3D unit\n"); return err; } + err = clk_prepare_enable(gr3d->clk); + if (err < 0) { + dev_err(&pdev->dev, "failed to enable 3D unit clock\n"); + return err; + } + if (gr3d->clk_secondary) { - err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D1, - gr3d->clk_secondary, - gr3d->rst_secondary); + err = gr3d_powergate_on(pdev, TEGRA_POWERGATE_3D1, + gr3d->clk_secondary, + gr3d->rst_secondary); if (err < 0) { dev_err(&pdev->dev, "failed to power up secondary 3D unit\n"); return err; } + + err = clk_prepare_enable(gr3d->clk_secondary); + if (err < 0) { + dev_err(&pdev->dev, + "failed to enable secondary 3D unit clock\n"); + return err; + } } INIT_LIST_HEAD(&gr3d->client.base.list); @@ -338,12 +380,13 @@ static int gr3d_remove(struct platform_device *pdev) } if (gr3d->clk_secondary) { - tegra_powergate_power_off(TEGRA_POWERGATE_3D1); clk_disable_unprepare(gr3d->clk_secondary); + gr3d_powergate_off(pdev, TEGRA_POWERGATE_3D1, + gr3d->clk_secondary, gr3d->rst_secondary); } - tegra_powergate_power_off(TEGRA_POWERGATE_3D); clk_disable_unprepare(gr3d->clk); + gr3d_powergate_off(pdev, TEGRA_POWERGATE_3D, gr3d->clk, gr3d->rst); return 0; }