From patchwork Mon Jul 13 12:39:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 6779121 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B3638C05AC for ; Mon, 13 Jul 2015 12:45:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B899F2055A for ; Mon, 13 Jul 2015 12:45:26 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A418C20528 for ; Mon, 13 Jul 2015 12:45:25 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZEd55-0002LY-2z; Mon, 13 Jul 2015 12:43:35 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZEd3B-0006Ut-Og for linux-arm-kernel@lists.infradead.org; Mon, 13 Jul 2015 12:41:38 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 13 Jul 2015 05:41:51 -0700 Received: from hqemhub02.nvidia.com ([172.20.150.31]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 13 Jul 2015 05:40:19 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 13 Jul 2015 05:40:19 -0700 Received: from jonathanh-lm.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.342.0; Mon, 13 Jul 2015 05:41:20 -0700 From: Jon Hunter To: Stephen Warren , Thierry Reding , Alexandre Courbot , Philipp Zabel , Peter De Schrijver , Prashant Gaikwad , =?UTF-8?q?Terje=20Bergstr=C3=B6m?= , Hans de Goede , Tejun Heo Subject: [PATCH V3 17/19] ARM: tegra: Add PM domain device nodes to Tegra124 DT Date: Mon, 13 Jul 2015 13:39:55 +0100 Message-ID: <1436791197-32358-18-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1436791197-32358-1-git-send-email-jonathanh@nvidia.com> References: <1436791197-32358-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150713_054137_838888_DE48C88E X-CRM114-Status: GOOD ( 10.59 ) X-Spam-Score: -8.3 (--------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Ulf Hansson , Vince Hsu , Kevin Hilman , linux-pm@vger.kernel.org, "Rafael J. Wysocki" , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add tegra124 pm-domains provider and consumer nodes. Signed-off-by: Jon Hunter --- arch/arm/boot/dts/tegra124.dtsi | 80 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 87318a72f615..3573bb079791 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -40,6 +41,8 @@ 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + power-domains = <&pd_pcie>; + clocks = <&tegra_car TEGRA124_CLK_PCIE>, <&tegra_car TEGRA124_CLK_AFI>, <&tegra_car TEGRA124_CLK_PLL_E>, @@ -99,6 +102,7 @@ compatible = "nvidia,tegra124-dc"; reg = <0x0 0x54200000 0x0 0x00040000>; interrupts = ; + power-domains = <&pd_dc>; clocks = <&tegra_car TEGRA124_CLK_DISP1>, <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "dc", "parent"; @@ -114,6 +118,7 @@ compatible = "nvidia,tegra124-dc"; reg = <0x0 0x54240000 0x0 0x00040000>; interrupts = ; + power-domains = <&pd_dcb>; clocks = <&tegra_car TEGRA124_CLK_DISP2>, <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "dc", "parent"; @@ -141,6 +146,7 @@ compatible = "nvidia,tegra124-sor"; reg = <0x0 0x54540000 0x0 0x00040000>; interrupts = ; + power-domains = <&pd_sor>; clocks = <&tegra_car TEGRA124_CLK_SOR0>, <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, <&tegra_car TEGRA124_CLK_PLL_DP>, @@ -155,6 +161,7 @@ compatible = "nvidia,tegra124-dpaux"; reg = <0x0 0x545c0000 0x0 0x00040000>; interrupts = ; + power-domains = <&pd_sor>; clocks = <&tegra_car TEGRA124_CLK_DPAUX>, <&tegra_car TEGRA124_CLK_PLL_DP>; clock-names = "dpaux", "parent"; @@ -184,6 +191,7 @@ interrupts = , ; interrupt-names = "stall", "nonstall"; + power-domains = <&pd_gpu>; clocks = <&tegra_car TEGRA124_CLK_GPU>, <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; clock-names = "gpu", "pwr"; @@ -573,6 +581,76 @@ reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + + pm-domains { + pd_gpu: gpu-power-domain { + clocks = <&tegra_car TEGRA124_CLK_GPU>, + <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; + resets = <&tegra_car 184>; + nvidia,powergate = ; + nvidia,swgroups = <&mc TEGRA_SWGROUP_GPU>; + #nvidia,swgroup-cells = <1>; + #power-domain-cells = <0>; + }; + + pd_pcie: pcie-power-domain { + clocks = <&tegra_car TEGRA124_CLK_PCIE>, + <&tegra_car TEGRA124_CLK_AFI>; + resets = <&tegra_car 70>, + <&tegra_car 72>; + nvidia,powergate = ; + nvidia,swgroups = <&mc TEGRA_SWGROUP_AFI>; + #nvidia,swgroup-cells = <1>; + #power-domain-cells = <0>; + }; + + pd_sata: sata-power-domain { + clocks = <&tegra_car TEGRA124_CLK_SATA>, + <&tegra_car TEGRA124_CLK_SATA_OOB>, + <&tegra_car TEGRA124_CLK_CML1>; + resets = <&tegra_car 124>, + <&tegra_car 123>, + <&tegra_car 129>; + nvidia,powergate = ; + nvidia,swgroups = <&mc TEGRA_SWGROUP_SATA>; + #nvidia,swgroup-cells = <1>; + #power-domain-cells = <0>; + }; + + pd_sor: sor-power-domain { + clocks = <&tegra_car TEGRA124_CLK_SOR0>, + <&tegra_car TEGRA124_CLK_DSIA>, + <&tegra_car TEGRA124_CLK_DSIB>, + <&tegra_car TEGRA124_CLK_HDMI>, + <&tegra_car TEGRA124_CLK_MIPI_CAL>, + <&tegra_car TEGRA124_CLK_DPAUX>; + resets = <&tegra_car 182>, + <&tegra_car 48>, + <&tegra_car 82>, + <&tegra_car 51>, + <&tegra_car 56>; + nvidia,powergate = ; + #power-domain-cells = <0>; + + pd_dc: dc-power-domain { + clocks = <&tegra_car TEGRA124_CLK_DISP1>; + resets = <&tegra_car 27>; + nvidia,powergate = ; + nvidia,swgroups = <&mc TEGRA_SWGROUP_DC>; + #nvidia,swgroup-cells = <1>; + #power-domain-cells = <0>; + + pd_dcb: dcb-power-domain { + clocks = <&tegra_car TEGRA124_CLK_DISP2>; + resets = <&tegra_car 26>; + nvidia,powergate = ; + nvidia,swgroups = <&mc TEGRA_SWGROUP_DCB>; + #nvidia,swgroup-cells = <1>; + #power-domain-cells = <0>; + }; + }; + }; + }; }; fuse@0,7000f800 { @@ -621,6 +699,8 @@ <&tegra_car 129>; reset-names = "sata", "sata-oob", "sata-cold"; + power-domains = <&pd_sata>; + phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; phy-names = "sata-phy";