From patchwork Mon Jul 13 12:39:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 6778961 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8E15E9F380 for ; Mon, 13 Jul 2015 12:43:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A5C8D2055A for ; Mon, 13 Jul 2015 12:43:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CC3FC20528 for ; Mon, 13 Jul 2015 12:43:03 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZEd2k-0006MV-DU; Mon, 13 Jul 2015 12:41:10 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZEd2T-00067S-Sb for linux-arm-kernel@lists.infradead.org; Mon, 13 Jul 2015 12:40:54 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 13 Jul 2015 05:41:06 -0700 Received: from hqemhub02.nvidia.com ([172.20.150.31]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 13 Jul 2015 05:39:34 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 13 Jul 2015 05:39:34 -0700 Received: from jonathanh-lm.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.342.0; Mon, 13 Jul 2015 05:40:35 -0700 From: Jon Hunter To: Stephen Warren , Thierry Reding , Alexandre Courbot , Philipp Zabel , Peter De Schrijver , Prashant Gaikwad , =?UTF-8?q?Terje=20Bergstr=C3=B6m?= , Hans de Goede , Tejun Heo Subject: [PATCH V3 05/19] memory: tegra: add flush operation for Tegra124 memory clients Date: Mon, 13 Jul 2015 13:39:43 +0100 Message-ID: <1436791197-32358-6-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1436791197-32358-1-git-send-email-jonathanh@nvidia.com> References: <1436791197-32358-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150713_054053_948925_82AA6E81 X-CRM114-Status: GOOD ( 11.55 ) X-Spam-Score: -8.3 (--------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Ulf Hansson , Vince Hsu , Kevin Hilman , linux-pm@vger.kernel.org, "Rafael J. Wysocki" , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Vince Hsu This patch adds the hot reset register table and flush related callback functions for Tegra124. Signed-off-by: Vince Hsu [jonathanh@nvidia.com: Removed tegra_mc_ops and added metastable_flush_reads.] Signed-off-by: Jon Hunter --- drivers/memory/tegra/tegra124.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c index 966e1557e6f4..a24993db14ed 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -1002,6 +1002,34 @@ static const struct tegra_smmu_swgroup tegra124_swgroups[] = { }; #ifdef CONFIG_ARCH_TEGRA_124_SOC + +static struct tegra_mc_flush tegra124_mc_flush[] = { + {TEGRA_SWGROUP_AFI, 0x200, 0x204, 0}, + {TEGRA_SWGROUP_AVPC, 0x200, 0x204, 1}, + {TEGRA_SWGROUP_DC, 0x200, 0x204, 2}, + {TEGRA_SWGROUP_DCB, 0x200, 0x204, 3}, + {TEGRA_SWGROUP_HC, 0x200, 0x204, 6}, + {TEGRA_SWGROUP_HDA, 0x200, 0x204, 7}, + {TEGRA_SWGROUP_ISP2, 0x200, 0x204, 8}, + {TEGRA_SWGROUP_MPCORE, 0x200, 0x204, 9}, + {TEGRA_SWGROUP_MPCORELP, 0x200, 0x204, 10}, + {TEGRA_SWGROUP_MSENC, 0x200, 0x204, 11}, + {TEGRA_SWGROUP_PPCS, 0x200, 0x204, 14}, + {TEGRA_SWGROUP_SATA, 0x200, 0x204, 15}, + {TEGRA_SWGROUP_VDE, 0x200, 0x204, 16}, + {TEGRA_SWGROUP_VI, 0x200, 0x204, 17}, + {TEGRA_SWGROUP_VIC, 0x200, 0x204, 18}, + {TEGRA_SWGROUP_XUSB_HOST, 0x200, 0x204, 19}, + {TEGRA_SWGROUP_XUSB_DEV, 0x200, 0x204, 20}, + {TEGRA_SWGROUP_TSEC, 0x200, 0x204, 22}, + {TEGRA_SWGROUP_SDMMC1A, 0x200, 0x204, 29}, + {TEGRA_SWGROUP_SDMMC2A, 0x200, 0x204, 30}, + {TEGRA_SWGROUP_SDMMC3A, 0x200, 0x204, 31}, + {TEGRA_SWGROUP_SDMMC4A, 0x970, 0x974, 0}, + {TEGRA_SWGROUP_ISP2B, 0x970, 0x974, 1}, + {TEGRA_SWGROUP_GPU, 0x970, 0x974, 2}, +}; + static void tegra124_flush_dcache(struct page *page, unsigned long offset, size_t size) { @@ -1035,6 +1063,9 @@ const struct tegra_mc_soc tegra124_mc_soc = { .smmu = &tegra124_smmu_soc, .emem_regs = tegra124_mc_emem_regs, .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs), + .flushes = tegra124_mc_flush, + .num_flushes = ARRAY_SIZE(tegra124_mc_flush), + .metastable_flush_reads = MC_FLUSH_METASTABLE_READS, }; #endif /* CONFIG_ARCH_TEGRA_124_SOC */