From patchwork Mon Jul 13 12:39:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 6779011 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8004AC05AC for ; Mon, 13 Jul 2015 12:43:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7F8002055D for ; Mon, 13 Jul 2015 12:43:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 871AC20528 for ; Mon, 13 Jul 2015 12:43:30 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZEd3O-0007Jh-ND; Mon, 13 Jul 2015 12:41:50 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZEd2c-0006AL-Nr for linux-arm-kernel@lists.infradead.org; Mon, 13 Jul 2015 12:41:03 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 13 Jul 2015 05:41:11 -0700 Received: from hqemhub02.nvidia.com ([172.20.150.31]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 13 Jul 2015 05:39:45 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 13 Jul 2015 05:39:45 -0700 Received: from jonathanh-lm.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.342.0; Mon, 13 Jul 2015 05:40:46 -0700 From: Jon Hunter To: Stephen Warren , Thierry Reding , Alexandre Courbot , Philipp Zabel , Peter De Schrijver , Prashant Gaikwad , =?UTF-8?q?Terje=20Bergstr=C3=B6m?= , Hans de Goede , Tejun Heo Subject: [PATCH V3 08/19] soc: tegra: pmc: Clean-up PMC helper functions Date: Mon, 13 Jul 2015 13:39:46 +0100 Message-ID: <1436791197-32358-9-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1436791197-32358-1-git-send-email-jonathanh@nvidia.com> References: <1436791197-32358-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150713_054102_800766_53008D80 X-CRM114-Status: GOOD ( 19.61 ) X-Spam-Score: -8.3 (--------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Ulf Hansson , Vince Hsu , Kevin Hilman , linux-pm@vger.kernel.org, "Rafael J. Wysocki" , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The following clean-ups have been made to the PMC code: 1. Add a macro for determining the state of a PMC powergate 2. Use the readx_poll_timeout() function instead of implementing a local polling loop with a timeout. 3. Use a case-statement in the function that removes the powergate clamp instead of multiple if-statements to improve readability. Signed-off-by: Jon Hunter --- drivers/soc/tegra/pmc.c | 72 ++++++++++++++++++++++++------------------------- 1 file changed, 35 insertions(+), 37 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index c0635bdd4ee3..180d434deec5 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -56,6 +57,8 @@ #define PWRGATE_TOGGLE_START (1 << 8) #define REMOVE_CLAMPING 0x34 +#define REMOVE_CLAMPING_VDEC (1 << 3) +#define REMOVE_CLAMPING_PCIE (1 << 4) #define PWRGATE_STATUS 0x38 @@ -101,6 +104,8 @@ #define GPU_RG_CNTRL 0x2d4 +#define PMC_PWRGATE_STATE(val, id) (!!(val & BIT(id))) + struct tegra_pmc_soc { unsigned int num_powergates; const char *const *powergates; @@ -177,15 +182,14 @@ static void tegra_pmc_writel(u32 value, unsigned long offset) */ static int tegra_powergate_set(int id, bool new_state, bool wait) { - unsigned long timeout; - bool status; int ret = 0; + u32 val; mutex_lock(&pmc->powergates_lock); - status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id); + val = tegra_pmc_readl(PWRGATE_STATUS); - if (status == new_state) { + if (PMC_PWRGATE_STATE(val, id) == new_state) { mutex_unlock(&pmc->powergates_lock); return 0; } @@ -193,17 +197,9 @@ static int tegra_powergate_set(int id, bool new_state, bool wait) tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); if (wait) { - timeout = jiffies + msecs_to_jiffies(100); - ret = -ETIMEDOUT; - - while (time_before(jiffies, timeout)) { - status = !!(tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)); - if (status == new_state) { - ret = 0; - break; - } - udelay(10); - } + ret = readx_poll_timeout(tegra_pmc_readl, PWRGATE_STATUS, + val, PMC_PWRGATE_STATE(val, id) == new_state, + 10, 100000); } mutex_unlock(&pmc->powergates_lock); @@ -242,13 +238,10 @@ EXPORT_SYMBOL(tegra_powergate_power_off); */ int tegra_powergate_is_powered(int id) { - u32 status; - if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates) return -EINVAL; - status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id); - return !!status; + return PMC_PWRGATE_STATE(tegra_pmc_readl(PWRGATE_STATUS), id); } /** @@ -257,34 +250,39 @@ int tegra_powergate_is_powered(int id) */ int tegra_powergate_remove_clamping(int id) { - u32 mask; + u32 val, reg; if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates) return -EINVAL; /* - * On Tegra124 and later, the clamps for the GPU are controlled by a - * separate register (with different semantics). + * In most cases the bit for removing the IO clamping is the same as + * the powergate partition ID, however, this is not always the case. + * Furthermore, on Tegra124 and later, the clamps for the GPU are + * controlled by a separate register (with different semantics). The + * following case-statement handles these exceptions. */ - if (id == TEGRA_POWERGATE_3D) { + val = 1 << id; + reg = REMOVE_CLAMPING; + + switch (id) { + case TEGRA_POWERGATE_3D: if (pmc->soc->has_gpu_clamps) { - tegra_pmc_writel(0, GPU_RG_CNTRL); - return 0; + val = 0; + reg = GPU_RG_CNTRL; } + break; + case TEGRA_POWERGATE_VDEC: + val = REMOVE_CLAMPING_VDEC; + break; + case TEGRA_POWERGATE_PCIE: + val = REMOVE_CLAMPING_PCIE; + break; + default: + break; } - /* - * Tegra 2 has a bug where PCIE and VDE clamping masks are - * swapped relatively to the partition ids - */ - if (id == TEGRA_POWERGATE_VDEC) - mask = (1 << TEGRA_POWERGATE_PCIE); - else if (id == TEGRA_POWERGATE_PCIE) - mask = (1 << TEGRA_POWERGATE_VDEC); - else - mask = (1 << id); - - tegra_pmc_writel(mask, REMOVE_CLAMPING); + tegra_pmc_writel(val, reg); return 0; }