@@ -1078,6 +1078,10 @@ config ARM_ERRATA_430973
and also flushes the branch target cache at every context switch.
Note that setting specific bits in the ACTLR register may not be
available in non-secure mode.
+ Instead of enabling this option, it is recommended to enable the
+ workaround by setting the IBE bit from the bootloader, since the
+ BTB/BTAC operations are always executed for context switches on
+ Cortex-A8.
config ARM_ERRATA_458693
bool "ARM errata: Processor deadlock when a false hazard is created"
The Errata 430973 workaround config option only enables the IBE bit, which should be done by the bootloader if possible. Signed-off-by: Sebastian Reichel <sre@kernel.org> --- arch/arm/Kconfig | 4 ++++ 1 file changed, 4 insertions(+)