From patchwork Thu Jul 23 22:51:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moritz Fischer X-Patchwork-Id: 6856371 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 356399F380 for ; Thu, 23 Jul 2015 22:55:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 33BEE2064E for ; Thu, 23 Jul 2015 22:55:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1D5142064D for ; Thu, 23 Jul 2015 22:55:55 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZIPNS-00005c-U0; Thu, 23 Jul 2015 22:54:10 +0000 Received: from mail-pa0-f51.google.com ([209.85.220.51]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZIPL2-0008HW-2J for linux-arm-kernel@lists.infradead.org; Thu, 23 Jul 2015 22:51:40 +0000 Received: by pabkd10 with SMTP id kd10so3247349pab.2 for ; Thu, 23 Jul 2015 15:51:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=p7H+SzSZThGEkiCvntya8clS6hl16+Jyyqz7g0YzKc8=; b=MmZCKsWEsu8/PQwnf1QTIk0Me61DQIY5hG1Vkv9SwKQU3AKDGufXLtr+Rn0sz3V2xq 2KBP4+jwozcmZPNCd/aaMxl6Fd+7/oaJ0CEB9g7FAjEB30snJjIYA/sNGFV8cD874DvP CjGdSREVcNFpnW852VRgJqYhA7CgU0AEOu6pk5M7NFjFNyyzJb40gTJ76tq2fdANjxfR QuNDwqCH02OL9Jir6fF9tM9ypLN8AgoCt7sI6aBzrQ+qaFh6s0kWxNTSsEitJ6fhvEe+ kJRANzoRKl9OUkp8mY0hQuY7IzwHY3fcqvrXbD6mdUOQt8XPcWebU8eoK8V0c4ZRydUQ kcsQ== X-Gm-Message-State: ALoCoQmN9pWiYQQJIN+cenk4YVD4qiPgVTyOZpToqbLIOU30OB7DIYQsZvZdsAZrt+hqXbNJpPSy X-Received: by 10.70.54.7 with SMTP id f7mr23103204pdp.75.1437691881534; Thu, 23 Jul 2015 15:51:21 -0700 (PDT) Received: from fenrir.amer.corp.natinst.com (209-234-137-234.static.twtelecom.net. [209.234.137.234]) by smtp.gmail.com with ESMTPSA id so5sm10881448pab.37.2015.07.23.15.51.19 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Jul 2015 15:51:19 -0700 (PDT) From: Moritz Fischer To: p.zabel@pengutronix.de Subject: [RFC 3/3] reset: reset-zynq-pl: Adding support for Xilinx Zynq PL reset. Date: Thu, 23 Jul 2015 15:51:02 -0700 Message-Id: <1437691862-21312-4-git-send-email-moritz.fischer@ettus.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1437691862-21312-1-git-send-email-moritz.fischer@ettus.com> References: <1437691862-21312-1-git-send-email-moritz.fischer@ettus.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150723_155140_200301_F09493D5 X-CRM114-Status: GOOD ( 19.32 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, Moritz Fischer , michal.simek@xilinx.com, soren.brinkmann@xilinx.com, linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Zynq PL reset controller allows to control the 4 FCLK{0..3}_RESETN signals that can be used to reset custom IP in the PL. Signed-off-by: Moritz Fischer --- drivers/reset/Makefile | 1 + drivers/reset/reset-zynq-pl.c | 142 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 143 insertions(+) create mode 100644 drivers/reset/reset-zynq-pl.c diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 157d421..5c86f92 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o obj-$(CONFIG_ARCH_STI) += sti/ +obj-$(CONFIG_ARCH_ZYNQ) += reset-zynq-pl.o diff --git a/drivers/reset/reset-zynq-pl.c b/drivers/reset/reset-zynq-pl.c new file mode 100644 index 0000000..3e04ab0 --- /dev/null +++ b/drivers/reset/reset-zynq-pl.c @@ -0,0 +1,142 @@ +/* + * Xilinx Zynq PL Reset Controller + * + * Copyright (c) 2015, National Instruments Corp. + * Author: Moritz Fischer + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Offsets into SLCR regmap */ +#define SLCR_FPGA_RST_CTRL_OFFSET 0x240 /* FPGA Software Reset Control */ + +struct zynq_pl_reset_data { + struct regmap *slcr; + struct reset_controller_dev rcdev; +}; + +static int zynq_pl_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct zynq_pl_reset_data *priv = container_of(rcdev, + struct zynq_pl_reset_data, + rcdev); + + int offset = id % BITS_PER_LONG; + + regmap_update_bits(priv->slcr, + SLCR_FPGA_RST_CTRL_OFFSET, + BIT(offset), + BIT(offset)); + + return 0; +} + +static int zynq_pl_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct zynq_pl_reset_data *priv = container_of(rcdev, + struct zynq_pl_reset_data, + rcdev); + + int offset = id % BITS_PER_LONG; + + regmap_update_bits(priv->slcr, + SLCR_FPGA_RST_CTRL_OFFSET, + BIT(offset), + ~BIT(offset)); + + return 0; +} + +static int zynq_pl_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct zynq_pl_reset_data *priv = container_of(rcdev, + struct zynq_pl_reset_data, + rcdev); + int offset = id % BITS_PER_LONG; + u32 reg; + + regmap_read(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, ®); + + return !(reg & BIT(offset)); +} + +static const struct reset_control_ops zynq_pl_reset_ops = { + .assert = zynq_pl_reset_assert, + .deassert = zynq_pl_reset_deassert, + .status = zynq_pl_reset_status, +}; + +static int zynq_pl_reset_probe(struct platform_device *pdev) +{ + struct zynq_pl_reset_data *priv; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + platform_set_drvdata(pdev, priv); + + priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "syscon"); + if (IS_ERR(priv->slcr)) { + dev_err(&pdev->dev, "unable to get zynq-slcr regmap"); + return PTR_ERR(priv->slcr); + } + + priv->rcdev.owner = THIS_MODULE; + priv->rcdev.nr_resets = BITS_PER_LONG; + priv->rcdev.ops = &zynq_pl_reset_ops; + priv->rcdev.of_node = pdev->dev.of_node; + reset_controller_register(&priv->rcdev); + + return 0; +} + +static int zynq_pl_reset_remove(struct platform_device *pdev) +{ + struct zynq_pl_reset_data *priv = platform_get_drvdata(pdev); + + reset_controller_unregister(&priv->rcdev); + + return 0; +} + +static const struct of_device_id zynq_pl_reset_dt_ids[] = { + { .compatible = "xlnx,zynq-reset-pl", }, + { /* sentinel */ }, +}; + +static struct platform_driver zynq_pl_reset_driver = { + .probe = zynq_pl_reset_probe, + .remove = zynq_pl_reset_remove, + .driver = { + .name = "zynq-pl-reset", + .of_match_table = zynq_pl_reset_dt_ids, + }, +}; +module_platform_driver(zynq_pl_reset_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Moritz Fischer "); +MODULE_DESCRIPTION("Zynq PL Reset Controller Driver"); +MODULE_ALIAS("reset:zynq-pl");