From patchwork Sat Jul 25 00:21:22 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moritz Fischer X-Patchwork-Id: 6863361 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 17DA3C05AC for ; Sat, 25 Jul 2015 00:24:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 10B2D20582 for ; Sat, 25 Jul 2015 00:24:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 106A3204D6 for ; Sat, 25 Jul 2015 00:24:16 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZInEB-0006QL-CH; Sat, 25 Jul 2015 00:22:11 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZInE8-0006Q2-TV for linux-arm-kernel@bombadil.infradead.org; Sat, 25 Jul 2015 00:22:09 +0000 Received: from mail-pa0-f42.google.com ([209.85.220.42]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZInE4-0005xA-Ni for linux-arm-kernel@lists.infradead.org; Sat, 25 Jul 2015 00:22:06 +0000 Received: by pacan13 with SMTP id an13so21877802pac.1 for ; Fri, 24 Jul 2015 17:21:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=POGdlWeWyYKzSGCTrl9m4TeEVdBeU2TIJhVW0p5bYwc=; b=O3e4s71pe4BMMRKjp50rqOsXpdCSk1XQKOhnxdDBN3i6Y3F3XyZ5+knnBCmy7iM1X7 FLrR1ssrf3wdG5TAl6dicK6r8OAk9TlHLFW4MUreD/eRE3ugLFLldF1nf762qWMs9bWm WMy0y3b43/lGOakZ8hmeGHlp7wbpZ0Up0OxuIXBWdn6pds5P5XvrlMJSVStCtptOhA9R 9tVpIxDXrZwzqcmSXaLZCTTivlPDOE/kE5XchQ+jrxtgY5Od+HhfBoaz46ogK67KdYLG CMY6GdsmXBzFTdgeo8INKDHidfZdySxkrFZRyn3NJ6SLCT5T9OH+vf7FFoXW6X/tNP5s cYKg== X-Gm-Message-State: ALoCoQm2ZiPuUg2daNCB/FkwHy1v1EO406odl/Rn121LA37FAEZy4KP6bhXuimZaX1H6MpouLB2k X-Received: by 10.66.63.8 with SMTP id c8mr37863988pas.122.1437783701311; Fri, 24 Jul 2015 17:21:41 -0700 (PDT) Received: from fenrir.amer.corp.natinst.com (209-234-137-234.static.twtelecom.net. [209.234.137.234]) by smtp.gmail.com with ESMTPSA id wv4sm16704510pac.2.2015.07.24.17.21.39 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Jul 2015 17:21:40 -0700 (PDT) From: Moritz Fischer To: p.zabel@pengutronix.de Subject: [RFCv2 3/3] reset: reset-zynq: Adding support for Xilinx Zynq reset controller. Date: Fri, 24 Jul 2015 17:21:22 -0700 Message-Id: <1437783682-13632-4-git-send-email-moritz.fischer@ettus.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1437783682-13632-1-git-send-email-moritz.fischer@ettus.com> References: <1437783682-13632-1-git-send-email-moritz.fischer@ettus.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150725_012204_924509_82B8249A X-CRM114-Status: GOOD ( 20.96 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Moritz Fischer , linux@arm.linux.org.uk, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, michal.simek@xilinx.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, galak@codeaurora.org, soren.brinkmann@xilinx.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds a reset controller driver to control the Xilinx Zynq SoC's various resets. Signed-off-by: Moritz Fischer --- drivers/reset/Makefile | 1 + drivers/reset/reset-zynq.c | 142 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 143 insertions(+) create mode 100644 drivers/reset/reset-zynq.c diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 157d421..3fe50e7 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o obj-$(CONFIG_ARCH_STI) += sti/ +obj-$(CONFIG_ARCH_ZYNQ) += reset-zynq.o diff --git a/drivers/reset/reset-zynq.c b/drivers/reset/reset-zynq.c new file mode 100644 index 0000000..05e37f8 --- /dev/null +++ b/drivers/reset/reset-zynq.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2015, National Instruments Corp. + * + * Xilinx Zynq Reset controller driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Offsets into SLCR regmap */ +#define SLCR_RST_CTRL_OFFSET 0x200 /* FPGA Software Reset Control */ + +#define NBANKS 18 + +struct zynq_reset_data { + struct regmap *slcr; + struct reset_controller_dev rcdev; +}; + +#define to_zynq_reset_data(p) \ + container_of((p), struct zynq_reset_data, rcdev) + +static int zynq_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct zynq_reset_data *priv = to_zynq_reset_data(rcdev); + + int bank = id / BITS_PER_LONG; + int offset = id % BITS_PER_LONG; + + regmap_update_bits(priv->slcr, + SLCR_RST_CTRL_OFFSET + (bank * 4), + BIT(offset), + BIT(offset)); + + return 0; +} + +static int zynq_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct zynq_reset_data *priv = to_zynq_reset_data(rcdev); + + int bank = id / BITS_PER_LONG; + int offset = id % BITS_PER_LONG; + + regmap_update_bits(priv->slcr, + SLCR_RST_CTRL_OFFSET + (bank * 4), + BIT(offset), + ~BIT(offset)); + + return 0; +} + +static int zynq_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct zynq_reset_data *priv = to_zynq_reset_data(rcdev); + + int bank = id / BITS_PER_LONG; + int offset = id % BITS_PER_LONG; + u32 reg; + + regmap_read(priv->slcr, SLCR_RST_CTRL_OFFSET + (bank * 4), ®); + + return !(reg & BIT(offset)); +} + +static const struct reset_control_ops zynq_reset_ops = { + .assert = zynq_reset_assert, + .deassert = zynq_reset_deassert, + .status = zynq_reset_status, +}; + +static int zynq_reset_probe(struct platform_device *pdev) +{ + struct zynq_reset_data *priv; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + platform_set_drvdata(pdev, priv); + + priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "syscon"); + if (IS_ERR(priv->slcr)) { + dev_err(&pdev->dev, "unable to get zynq-slcr regmap"); + return PTR_ERR(priv->slcr); + } + + priv->rcdev.owner = THIS_MODULE; + priv->rcdev.nr_resets = NBANKS * BITS_PER_LONG; + priv->rcdev.ops = &zynq_reset_ops; + priv->rcdev.of_node = pdev->dev.of_node; + reset_controller_register(&priv->rcdev); + + return 0; +} + +static int zynq_reset_remove(struct platform_device *pdev) +{ + struct zynq_reset_data *priv = platform_get_drvdata(pdev); + + reset_controller_unregister(&priv->rcdev); + + return 0; +} + +static const struct of_device_id zynq_reset_dt_ids[] = { + { .compatible = "xlnx,zynq-reset", }, + { /* sentinel */ }, +}; + +static struct platform_driver zynq_reset_driver = { + .probe = zynq_reset_probe, + .remove = zynq_reset_remove, + .driver = { + .name = "zynq-pl-reset", + .of_match_table = zynq_reset_dt_ids, + }, +}; +module_platform_driver(zynq_reset_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Moritz Fischer "); +MODULE_DESCRIPTION("Zynq Reset Controller Driver");