From patchwork Fri Jul 31 01:13:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moritz Fischer X-Patchwork-Id: 6907771 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 37D76C05AC for ; Fri, 31 Jul 2015 01:17:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5450020602 for ; Fri, 31 Jul 2015 01:17:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 76408205EA for ; Fri, 31 Jul 2015 01:17:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZKyuZ-0000Jx-Kh; Fri, 31 Jul 2015 01:14:59 +0000 Received: from mail-pa0-f49.google.com ([209.85.220.49]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZKyuK-0000Ea-Qf for linux-arm-kernel@lists.infradead.org; Fri, 31 Jul 2015 01:14:45 +0000 Received: by pachj5 with SMTP id hj5so31559233pac.3 for ; Thu, 30 Jul 2015 18:14:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1pDo+yBYTFkEY/ZfsmNupbOWXG4F96s/GptQQk8KAak=; b=DLHBF1BtpKhWG/JqM7GnnUPJ8KoCjZQeTYq6NpdhMRo8SFQXy/1aP3Up6k+aDeKY+E FfUvxVXznlEHaylzwCCgU9GqAqkHSHXwox682m9aMgYOkXf+xJUnVY+PRyh2+z2rOq1B IVpjYjwtON2tFxYXRP8XrC/25GRN+9cbut9rurDkJBpQO0l2Hmqzm1Ae6yux2vMfgXAv opIWYolxuE89ZzjTENG40kMGIFYEIzGmdJzhRoABOlb9G/4Sym1cOmqy76mMrm0Gm8/j dXq4TQ5HRsXMT/Tf2aA8LgpRAOZMTXXBKtIB0rN4Q0+L6DBej76/3vP1qC4k9vj2lwSv wj3w== X-Gm-Message-State: ALoCoQkxUqINuuwnSFre20A4ZIDU1TlDCAicSa+Fx3Zqgi4WRROQeHz9vaq2H1kI+nf01SCarNYM X-Received: by 10.66.157.195 with SMTP id wo3mr475016pab.17.1438305263918; Thu, 30 Jul 2015 18:14:23 -0700 (PDT) Received: from fenrir.amer.corp.natinst.com (209-234-137-234.static.twtelecom.net. [209.234.137.234]) by smtp.gmail.com with ESMTPSA id b4sm4288964pdn.42.2015.07.30.18.14.21 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Jul 2015 18:14:22 -0700 (PDT) From: Moritz Fischer To: p.zabel@pengutronix.de Subject: [RFCv3 1/4] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings. Date: Thu, 30 Jul 2015 18:13:54 -0700 Message-Id: <1438305237-18497-2-git-send-email-moritz.fischer@ettus.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1438305237-18497-1-git-send-email-moritz.fischer@ettus.com> References: <1438305237-18497-1-git-send-email-moritz.fischer@ettus.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150730_181444_890701_27F72D73 X-CRM114-Status: GOOD ( 12.85 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Moritz Fischer , linux@arm.linux.org.uk, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, michal.simek@xilinx.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, galak@codeaurora.org, soren.brinkmann@xilinx.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Moritz Fischer --- .../devicetree/bindings/reset/zynq-reset.txt | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt diff --git a/Documentation/devicetree/bindings/reset/zynq-reset.txt b/Documentation/devicetree/bindings/reset/zynq-reset.txt new file mode 100644 index 0000000..498c037a --- /dev/null +++ b/Documentation/devicetree/bindings/reset/zynq-reset.txt @@ -0,0 +1,68 @@ +Xilinx Zynq Reset Manager + +The Zynq AP-SoC has several different resets. + +See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets. + +Required properties: +- compatible: "xlnx,zynq-reset" +- reg: SLCR offset and size taken via syscon <0x200 0x48> +- syscon: <&slcr> + This should be a phandle to the Zynq's SLCR register. +- #reset-cells: Must be 1 + +The Zynq Reset Manager needs to be a childnode of the SLCR. + +Example: + rstc: rstc@200 { + compatible = "xlnx,zynq-reset"; + reg = <0x200 0x48>; + #reset-cells = <1>; + syscon = <&slcr>; + }; + +Reset outputs: + 0 : soft reset + 32 : ddr reset + 64 : topsw reset + 96 : dmac reset + 128: usb0 reset + 129: usb1 reset + 160: gem0 reset + 161: gem1 reset + 164: gem0 rx reset + 165: gem1 rx reset + 166: gem0 ref reset + 167: gem1 ref reset + 192: sdio0 reset + 193: sdio1 reset + 196: sdio0 ref reset + 197: sdio1 ref reset + 224: spi0 reset + 225: spi1 reset + 226: spi0 ref reset + 227: spi1 ref reset + 256: can0 reset + 257: can1 reset + 258: can0 ref reset + 259: can1 ref reset + 288: i2c0 reset + 289: i2c1 reset + 320: uart0 reset + 321: uart1 reset + 322: uart0 ref reset + 323: uart1 ref reset + 352: gpio reset + 384: lqspi reset + 385: qspi ref reset + 416: smc reset + 417: smc ref reset + 448: ocm reset + 512: fpga0 out reset + 513: fpga1 out reset + 514: fpga2 out reset + 515: fpga3 out reset + 544: a9 reset 0 + 545: a9 reset 1 + 552: peri reset +