From patchwork Fri Aug 7 09:31:12 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: huang lin X-Patchwork-Id: 6967241 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 02717C05AC for ; Fri, 7 Aug 2015 09:34:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F2C9620632 for ; Fri, 7 Aug 2015 09:34:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E54102062D for ; Fri, 7 Aug 2015 09:34:47 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZNe0n-0002My-2L; Fri, 07 Aug 2015 09:32:25 +0000 Received: from va-smtp01.263.net ([54.88.144.211]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZNe0j-0002Ij-MS; Fri, 07 Aug 2015 09:32:23 +0000 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by va-smtp01.263.net (Postfix) with ESMTP id F2E059F79B; Fri, 7 Aug 2015 17:31:51 +0800 (CST) X-RL-SENDER: hl@rock-chips.com X-SENDER-IP: 191.101.57.10 X-LOGIN-NAME: hl@rock-chips.com X-UNIQUE-TAG: <0594c1028fa3c90eac49b1b44197b092> X-ATTACHMENT-NUM: 0 X-SENDER: hl@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [191.101.57.10]) by va-smtp01.263.net (Postfix) whith SMTP id 8815YJ4GHD; Fri, 07 Aug 2015 17:31:57 +0800 (CST) From: Lin Huang To: heiko@sntech.de, dianders@chromium.org Subject: [PATCH v4 2/2] pinctrl: rockchip: only enable gpio clock when it setting Date: Fri, 7 Aug 2015 17:31:12 +0800 Message-Id: <1438939872-2116-2-git-send-email-hl@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1438939872-2116-1-git-send-email-hl@rock-chips.com> References: <1438939872-2116-1-git-send-email-hl@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150807_023222_038651_D177FED3 X-CRM114-Status: UNSURE ( 9.77 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lin Huang , linux-gpio@vger.kernel.org, linus.walleij@linaro.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP gpio can keep state even the clock disable, for save power consumption, only enable gpio clock when it setting Signed-off-by: Lin Huang Reviewed-by: Heiko Stuebner --- Changes in v4: -delete some unrelated new blank line drivers/pinctrl/pinctrl-rockchip.c | 55 +++++++++++++++++++++++++++++++++++--- 1 file changed, 51 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index cc2843a..c5246c0 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -945,6 +945,7 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, if (ret < 0) return ret; + clk_enable(bank->clk); spin_lock_irqsave(&bank->slock, flags); data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); @@ -956,6 +957,7 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); spin_unlock_irqrestore(&bank->slock, flags); + clk_disable(bank->clk); return 0; } @@ -1389,6 +1391,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) unsigned long flags; u32 data; + clk_enable(bank->clk); spin_lock_irqsave(&bank->slock, flags); data = readl(reg); @@ -1398,6 +1401,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) writel(data, reg); spin_unlock_irqrestore(&bank->slock, flags); + clk_disable(bank->clk); } /* @@ -1409,7 +1413,9 @@ static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); u32 data; + clk_enable(bank->clk); data = readl(bank->reg_base + GPIO_EXT_PORT); + clk_disable(bank->clk); data >>= offset; data &= 1; return data; @@ -1546,6 +1552,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) if (ret < 0) return ret; + clk_enable(bank->clk); spin_lock_irqsave(&bank->slock, flags); data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); @@ -1603,6 +1610,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) default: irq_gc_unlock(gc); spin_unlock_irqrestore(&bank->slock, flags); + clk_disable(bank->clk); return -EINVAL; } @@ -1611,6 +1619,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) irq_gc_unlock(gc); spin_unlock_irqrestore(&bank->slock, flags); + clk_disable(bank->clk); return 0; } @@ -1620,8 +1629,10 @@ static void rockchip_irq_suspend(struct irq_data *d) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct rockchip_pin_bank *bank = gc->private; + clk_enable(bank->clk); bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); + clk_disable(bank->clk); } static void rockchip_irq_resume(struct irq_data *d) @@ -1629,7 +1640,27 @@ static void rockchip_irq_resume(struct irq_data *d) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct rockchip_pin_bank *bank = gc->private; + clk_enable(bank->clk); irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); + clk_disable(bank->clk); +} + +static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct rockchip_pin_bank *bank = gc->private; + + clk_enable(bank->clk); + irq_gc_mask_clr_bit(d); +} + +void rockchip_irq_gc_mask_set_bit(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct rockchip_pin_bank *bank = gc->private; + + irq_gc_mask_set_bit(d); + clk_disable(bank->clk); } static int rockchip_interrupts_register(struct platform_device *pdev, @@ -1640,7 +1671,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev, unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; struct irq_chip_generic *gc; int ret; - int i; + int i, j; for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { if (!bank->valid) { @@ -1649,11 +1680,19 @@ static int rockchip_interrupts_register(struct platform_device *pdev, continue; } + ret = clk_enable(bank->clk); + if (ret) { + dev_err(&pdev->dev, "failed to enable clock for bank %s\n", + bank->name); + continue; + } + bank->domain = irq_domain_add_linear(bank->of_node, 32, &irq_generic_chip_ops, NULL); if (!bank->domain) { dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", bank->name); + clk_disable(bank->clk); continue; } @@ -1664,6 +1703,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev, dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", bank->name); irq_domain_remove(bank->domain); + clk_disable(bank->clk); continue; } @@ -1681,8 +1721,9 @@ static int rockchip_interrupts_register(struct platform_device *pdev, gc->chip_types[0].regs.mask = GPIO_INTMASK; gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; - gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; - gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; + gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit; + gc->chip_types[0].chip.irq_unmask = + rockchip_irq_gc_mask_clr_bit; gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; @@ -1691,6 +1732,12 @@ static int rockchip_interrupts_register(struct platform_device *pdev, irq_set_chained_handler_and_data(bank->irq, rockchip_irq_demux, bank); + + /* map the gpio irqs here, when the clock is still running */ + for (j = 0 ; j < 32 ; j++) + irq_create_mapping(bank->domain, j); + + clk_disable(bank->clk); } return 0; @@ -1808,7 +1855,7 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, if (IS_ERR(bank->clk)) return PTR_ERR(bank->clk); - return clk_prepare_enable(bank->clk); + return clk_prepare(bank->clk); } static const struct of_device_id rockchip_pinctrl_dt_match[];