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Tue, 11 Aug 2015 12:46:28 +0900 (KST) From: Chanwoo Choi To: s.nawrocki@samsung.com, tomasz.figa@gmail.com, kgene@kernel.org, k.kozlowski@samsung.com Subject: [PATCH 1/4] clk: samsung: exynos3250: Add UART2 clock Date: Tue, 11 Aug 2015 12:46:21 +0900 Message-id: <1439264784-30322-2-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.5.5 In-reply-to: <1439264784-30322-1-git-send-email-cw00.choi@samsung.com> References: <1439264784-30322-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFLMWRmVeSWpSXmKPExsWyRsSkSFek4GSowZJGfYvrX56zWsw/co7V 4vULQ4v+x6+ZLTY9vsZq8bHnHqvF5V1z2CxmnN/HZHHxlKvF4TftrBY/znSzWKza9YfRgcfj /Y1Wdo/Lfb1MHjtn3WX32LSqk81j85J6j74tqxg9Pm+SC2CP4rJJSc3JLEst0rdL4MqYc+sC a8EU6YolE7IbGE+KdTFyckgImEgcnnWRBcIWk7hwbz1bFyMXh5DACkaJd/+nssIU3Zh2nBUi MYtR4uebI+wQzhdGiQ9bD7KBVLEJaEnsf3EDyObgEBGIk2joEwKpYRZ4wyjxZEI7I0hcWMBO 4vQDsG0sAqoSZ+dfYwKxeQVcJU7f2MgGsUxBYtnymWCLOQXcJA7faAWrEQKquXOklxlkpoTA KXaJk6tWsUIMEpD4NvkQC8h8CQFZiU0HmCHmSEocXHGDZQKj8AJGhlWMoqkFyQXFSelFJnrF ibnFpXnpesn5uZsYgVFy+t+zCTsY7x2wPsQowMGoxMMr4HkyVIg1say4MvcQoynQhonMUqLJ +cBYzCuJNzQ2M7IwNTE1NjK3NFMS530t9TNYSCA9sSQ1OzW1ILUovqg0J7X4ECMTB6dUA2P7 ot+9PCHHdR5NSteKbZcr6f4iu0QzfuHNn0Lxme1HWWc85H3Gkdjsr6Jqd6TXqT1Ia8K/TwrP rC5PMfQ6UnmY5R/L/SmxopL877mTtnpVfpw3f05JzOFrvtwvI5weVAuy8G8JcT61wTwrJ7Lt W9E17uhQlom+spfkZ+tu+B/2e/Kk8Kc26UosxRmJhlrMRcWJAAT3KJaNAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOIsWRmVeSWpSXmKPExsVy+t9jQV2RgpOhBqcPalpc//Kc1WL+kXOs Fq9fGFr0P37NbLHp8TVWi48991gtLu+aw2Yx4/w+JouLp1wtDr9pZ7X4caabxWLVrj+MDjwe 72+0sntc7utl8tg56y67x6ZVnWwem5fUe/RtWcXo8XmTXAB7VAOjTUZqYkpqkUJqXnJ+SmZe uq2Sd3C8c7ypmYGhrqGlhbmSQl5ibqqtkotPgK5bZg7QnUoKZYk5pUChgMTiYiV9O0wTQkPc dC1gGiN0fUOC4HqMDNBAwhrGjDm3LrAWTJGuWDIhu4HxpFgXIyeHhICJxI1px1khbDGJC/fW s3UxcnEICcxilPj55gg7hPOFUeLD1oNsIFVsAloS+1/cALI5OEQE4iQa+oRAapgF3jBKPJnQ zggSFxawkzj9gAWknEVAVeLs/GtMIDavgKvE6Rsb2SCWKUgsWz4TbDGngJvE4RutYDVCQDV3 jvQyT2DkXcDIsIpRIrUguaA4KT3XMC+1XK84Mbe4NC9dLzk/dxMjOBKfSe1gPLjL/RCjAAej Eg+vgOfJUCHWxLLiytxDjBIczEoivK+cgEK8KYmVValF+fFFpTmpxYcYTYEOm8gsJZqcD0wS eSXxhsYmZkaWRuaGFkbG5krivLIbNocKCaQnlqRmp6YWpBbB9DFxcEo1MHpbzmvqn/a84MXR 5INrqpybJpaf4HqzQuisiMeCGmv2hzfZwn9xrV2rqLnHK3jWrbtTTzRntM4vjdm3cWkDr1nL gSKpjsA/fFlaKpFbuvKFJ0lP2Lo1vvOvtuOjd5+44o8cruL+JqInPDv6sl3Do+pvlScii9IW sx/xMHmatfHn3/rSwGuLPZVYijMSDbWYi4oTAZ1SOt/aAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150810_204652_157497_0E1BB2B1 X-CRM114-Status: GOOD ( 10.59 ) X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, cw00.choi@samsung.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos3250.c | 6 ++++++ include/dt-bindings/clock/exynos3250.h | 6 +++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index 538de66a759e..2105863a3ace 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -307,6 +307,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = { MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4), /* SRC_PERIL0 */ + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4), MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4), MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4), @@ -389,6 +390,7 @@ static struct samsung_div_clock div_clks[] __initdata = { DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), /* DIV_PERIL0 */ + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), @@ -551,6 +553,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre", GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0), + + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2", + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1", GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", @@ -648,6 +653,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0), GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0), GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0), + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0), GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0), GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0), }; diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index aab088d30199..89a7d97b002c 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -78,6 +78,7 @@ #define CLK_MOUT_CORE 58 #define CLK_MOUT_APLL 59 #define CLK_MOUT_ACLK_266_SUB 60 +#define CLK_MOUT_UART2 61 /* Dividers */ #define CLK_DIV_GPL 64 @@ -126,6 +127,7 @@ #define CLK_DIV_CORE 107 #define CLK_DIV_HPM 108 #define CLK_DIV_COPY 109 +#define CLK_DIV_UART2 110 /* Gates */ #define CLK_ASYNC_G3D 128 @@ -222,6 +224,7 @@ #define CLK_BLOCK_MFC 219 #define CLK_BLOCK_CAM 220 #define CLK_SMIES 221 +#define CLK_UART2 222 /* Special clocks */ #define CLK_SCLK_JPEG 224 @@ -248,12 +251,13 @@ #define CLK_SCLK_SPI0 245 #define CLK_SCLK_UART1 246 #define CLK_SCLK_UART0 247 +#define CLK_SCLK_UART2 248 /* * Total number of clocks of main CMU. * NOTE: Must be equal to last clock ID increased by one. */ -#define CLK_NR_CLKS 248 +#define CLK_NR_CLKS 249 /* * CMU DMC