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Tue, 11 Aug 2015 12:46:28 +0900 (KST) From: Chanwoo Choi To: s.nawrocki@samsung.com, tomasz.figa@gmail.com, kgene@kernel.org, k.kozlowski@samsung.com Subject: [PATCH 2/4] clk: samsung: exynos3250: Add MMC2 clock Date: Tue, 11 Aug 2015 12:46:22 +0900 Message-id: <1439264784-30322-3-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.5.5 In-reply-to: <1439264784-30322-1-git-send-email-cw00.choi@samsung.com> References: <1439264784-30322-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrNLMWRmVeSWpSXmKPExsWyRsSkSFek4GSowdZbZhbXvzxntZh/5Byr xesXhhb9j18zW2x6fI3V4mPPPVaLy7vmsFnMOL+PyeLiKVeLw2/aWS1+nOlmsVi16w+jA4/H +xut7B6X+3qZPHbOusvusWlVJ5vH5iX1Hn1bVjF6fN4kF8AexWWTkpqTWZZapG+XwJVx/Mh8 toJ/MhXPFn9ibGCcJNHFyMkhIWAicf3eISYIW0ziwr31bF2MXBxCAisYJf7suMEKU7Ru3gN2 iMQsRonpW86xQjhfGCU+bD3IBlLFJqAlsf/FDSCbg0NEIE6ioU8IpIZZ4A2jxJMJ7YwgNcIC thIH+2+zgNgsAqoS03Z8ZQSp5xVwldj0vhZimYLEsuUzwRZzCrhJHL7RCnadEFDJnSO9zCAz JQTOsUvcvfqZHWKOgMS3yYdYQOZICMhKbDrADDFHUuLgihssExiFFzAyrGIUTS1ILihOSi8y 0StOzC0uzUvXS87P3cQIjJPT/55N2MF474D1IUYBDkYlHl4Bz5OhQqyJZcWVuYcYTYE2TGSW Ek3OB0ZjXkm8obGZkYWpiamxkbmlmZI472upn8FCAumJJanZqakFqUXxRaU5qcWHGJk4OKUa GGN8/9x98djgf6SwsLbA5l/C3qscAnc2vfju1nBs4pPzW6VUt7+bOCH2+8MFLOVc/z2vXH8V lROU3CyzjDdK/JSW0K3OuyVsAawK8+VvfJ9hNqvl2xSJjvj4fJtb/+xYb82SbZkSk7xZ0WHe VyWVXx+WqKok+543DOdni/u8wLv7xWLek0KnJJRYijMSDbWYi4oTAZkbAECOAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrBIsWRmVeSWpSXmKPExsVy+t9jQV2RgpOhBqvfGFhc//Kc1WL+kXOs Fq9fGFr0P37NbLHp8TVWi48991gtLu+aw2Yx4/w+JouLp1wtDr9pZ7X4caabxWLVrj+MDjwe 72+0sntc7utl8tg56y67x6ZVnWwem5fUe/RtWcXo8XmTXAB7VAOjTUZqYkpqkUJqXnJ+SmZe uq2Sd3C8c7ypmYGhrqGlhbmSQl5ibqqtkotPgK5bZg7QnUoKZYk5pUChgMTiYiV9O0wTQkPc dC1gGiN0fUOC4HqMDNBAwhrGjONH5rMV/JOpeLb4E2MD4ySJLkZODgkBE4l18x6wQ9hiEhfu rWfrYuTiEBKYxSgxfcs5VgjnC6PEh60H2UCq2AS0JPa/uAFkc3CICMRJNPQJgdQwC7xhlHgy oZ0RpEZYwFbiYP9tFhCbRUBVYtqOr4wg9bwCrhKb3tdCLFOQWLZ8JiuIzSngJnH4RisTiC0E VHLnSC/zBEbeBYwMqxglUguSC4qT0nMN81LL9YoTc4tL89L1kvNzNzGCY/GZ1A7Gg7vcDzEK cDAq8fAKeJ4MFWJNLCuuzD3EKMHBrCTC+8oJKMSbklhZlVqUH19UmpNafIjRFOiuicxSosn5 wDSRVxJvaGxiZmRpZG5oYWRsriTOK7thc6iQQHpiSWp2ampBahFMHxMHp1QD417TgNqr89L1 Ins9hKJPvzdoiTY61/mn/HrezbcakZ+umarXeLf+sOcXyPt7Pd+sLvbTw80Cla921xzMivl/ uP1a5gXdeSf+uBcp5bBo3TadylvIx3zFztWw8dYHjiTl2u7jcff3Hp499xPXGpFtv1nFe6+z v5vmk64fHjxt2h+HHXvuB23fqsRSnJFoqMVcVJwIADO7shXbAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150810_204652_145285_DA27DF3E X-CRM114-Status: GOOD ( 11.71 ) X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, cw00.choi@samsung.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos3250.c | 9 +++++++++ include/dt-bindings/clock/exynos3250.h | 7 ++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index 2105863a3ace..2683cf03e656 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -303,6 +303,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = { /* SRC_FSYS */ MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4), + MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4), MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4), MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4), @@ -389,6 +390,11 @@ static struct samsung_div_clock div_clks[] __initdata = { CLK_SET_RATE_PARENT, 0), DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), + /* DIV_FSYS2 */ + DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8, + CLK_SET_RATE_PARENT, 0), + DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), + /* DIV_PERIL0 */ DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), @@ -539,6 +545,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi", GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre", + GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre", GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre", @@ -634,6 +642,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0), GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0), GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0), + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0), GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0), GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0), GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0), diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index 89a7d97b002c..fbc9ef61b191 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -79,6 +79,7 @@ #define CLK_MOUT_APLL 59 #define CLK_MOUT_ACLK_266_SUB 60 #define CLK_MOUT_UART2 61 +#define CLK_MOUT_MMC2 62 /* Dividers */ #define CLK_DIV_GPL 64 @@ -128,6 +129,8 @@ #define CLK_DIV_HPM 108 #define CLK_DIV_COPY 109 #define CLK_DIV_UART2 110 +#define CLK_DIV_MMC2_PRE 111 +#define CLK_DIV_MMC2 112 /* Gates */ #define CLK_ASYNC_G3D 128 @@ -225,6 +228,7 @@ #define CLK_BLOCK_CAM 220 #define CLK_SMIES 221 #define CLK_UART2 222 +#define CLK_SDMMC2 223 /* Special clocks */ #define CLK_SCLK_JPEG 224 @@ -252,12 +256,13 @@ #define CLK_SCLK_UART1 246 #define CLK_SCLK_UART0 247 #define CLK_SCLK_UART2 248 +#define CLK_SCLK_MMC2 249 /* * Total number of clocks of main CMU. * NOTE: Must be equal to last clock ID increased by one. */ -#define CLK_NR_CLKS 249 +#define CLK_NR_CLKS 250 /* * CMU DMC