From patchwork Wed Aug 19 02:55:20 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "majun (F)" X-Patchwork-Id: 7034661 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5AD23C05AD for ; Wed, 19 Aug 2015 03:01:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A3E0E2082A for ; Wed, 19 Aug 2015 03:01:49 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BB26F20826 for ; Wed, 19 Aug 2015 03:01:48 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZRtYk-0000QN-SJ; Wed, 19 Aug 2015 02:57:02 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZRtYe-0000Mo-3l for linux-arm-kernel@lists.infradead.org; Wed, 19 Aug 2015 02:56:57 +0000 Received: from 172.24.1.50 (EHLO szxeml425-hub.china.huawei.com) ([172.24.1.50]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CTJ05151; Wed, 19 Aug 2015 10:55:35 +0800 (CST) Received: from localhost (10.177.235.245) by szxeml425-hub.china.huawei.com (10.82.67.180) with Microsoft SMTP Server id 14.3.235.1; Wed, 19 Aug 2015 10:55:27 +0800 From: MaJun To: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 2/2] dt-binding:Documents of the mbigen bindings Date: Wed, 19 Aug 2015 10:55:20 +0800 Message-ID: <1439952920-2296-3-git-send-email-majun258@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1439952920-2296-1-git-send-email-majun258@huawei.com> References: <1439952920-2296-1-git-send-email-majun258@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.235.245] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150818_195657_068517_EBA57737 X-CRM114-Status: GOOD ( 15.13 ) X-Spam-Score: -4.6 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ma Jun Add the mbigen msi interrupt controller bindings document. Change since v3: --- Change the interrupt cells definition. --- Change the mbigen node definition. --- Add mbigen device node as sub node of mbigen. Signed-off-by: Ma Jun --- Documentation/devicetree/bindings/arm/mbigen.txt | 97 ++++++++++++++++++++++ 1 files changed, 97 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mbigen.txt diff --git a/Documentation/devicetree/bindings/arm/mbigen.txt b/Documentation/devicetree/bindings/arm/mbigen.txt new file mode 100644 index 0000000..8e1203b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mbigen.txt @@ -0,0 +1,97 @@ +Hisilicon mbigen device tree bindings. +======================================= + +Mbigen means: message based interrupt generator. + +MBI is kind of msi interrupt only used on Non-PCI devices. + +To reduce the wired interrupt number connected to GIC, +Hisilicon designed mbigen to collect and generate interrupt. + + +Non-pci devices can connect to mbigen and generate the +interrupt by writing ITS register. + +The mbigen chip and devices connect to mbigen have the following properties: + +Mbigen main node required properties: +------------------------------------------- +- compatible: Should be "hisilicon,mbigen-v2" +- interrupt controller: Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value is 4 now. + + The 1st cell is the device id. + The 2nd cell is the mbigen node number. This value should refer to the + vendor Soc specification. + The 3rd cell is the hardware pin number of the interrupt. + This value depends on the Soc design. + The 4th cell is the interrupt trigger type, encoded as follows: + 1 = edge triggered + 4 = level triggered + +- #mbigen-node-cells :Specifies the number of cells needed to encode an + mbigen node information. The value is 3 now. + + The 1st cell is the mbigen node number. + The 2nd cell is the interrupt numbers connected to. + The 3rd cell is the start value of pin offset. + +- reg: Specifies the base physical address and size of the Mbigen + registers. + +Sub-nodes: + +Mbigen has one or more mbigen device nodes which represents the devices +connected to this mbigen chip. + +These nodes must have the following properties: +- msi-parent: This property has two cells. + The 1st cell specifies the ITS this device connected. + The 2nd cell specifies the device id. +- nr-interrupts:Specifies the total number of interrupt this device has. +- mbigen_node: Specifies the information of mbigen nodes this device + connected.Some devices with many interrupts maybe connects with several + mbigen nodes. + +Examples: + + mbigen_dsa: interrupt-controller@c0080000 { + compatible = "hisilicon,mbigen-v2"; + interrupt-controller; + #interrupt-cells = <5>; + #mbigen-node-cells = <3>; + reg = <0xc0080000 0x10000>; + + mbigen_device_01 { + msi-parent = <&its 0x40b1c>; + nr-interrupts = <9>; + mbigen_node = <1 2 0>, + <3 2 4>, + <4 5 0>; + } + + mbigen_device_02 { + msi-parent = <&its 0x40b1d>; + nr-interrupts = <3>; + mbigen_node = <6 3 0>; + interrupt-controller; + } + }; + +Device connect to mbigen required properties: +---------------------------------------------------- +-interrupt-parent: Specifies the mbigen node which device connected. +-interrupts:specifies the interrupt source.The first cell is hwirq num, the + second number is trigger type. + +Examples: + smmu_dsa { + compatible = "arm,smmu-v3"; + reg = <0x0 0xc0040000 0x0 0x20000>; + interrupt-parent = <&mbigen_dsa>; + interrupts = <0x40b20 6 78 1>, + <0x40b20 6 79 1>, + <0x40b20 6 80 1>; + }; +