From patchwork Tue Sep 1 19:32:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Hiremath X-Patchwork-Id: 7106711 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 681BE9F1CD for ; Tue, 1 Sep 2015 19:37:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 81A66205EC for ; Tue, 1 Sep 2015 19:37:57 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 49A38205F1 for ; Tue, 1 Sep 2015 19:37:56 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZWrLe-0000ym-RW; Tue, 01 Sep 2015 19:36:02 +0000 Received: from mail-pa0-f51.google.com ([209.85.220.51]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZWrLU-0000nd-Jn for linux-arm-kernel@lists.infradead.org; Tue, 01 Sep 2015 19:35:53 +0000 Received: by padhy1 with SMTP id hy1so5422048pad.1 for ; Tue, 01 Sep 2015 12:35:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XG6h7T/4vSSfe6GGMT686tHDlX3P+FhLJ+Qfsw06oVc=; b=kCINtDWlkPtvqdeDcNnonbiP1GDSry8jMWSouZ1+CMBeuKZZU4dhUiDkK65dp1tAfa 8eTaGRQCI4Nu1YlCQsNKAz+o0wc/h4ucASEJzJobU0yuSwIFl8a234ZMrIrOjjPwDltu PpU6QVTj2iTwY8ZW3VXXQ/W0t/YP/wJPeQ139h5zD2CaTwn2LMq7j3uFjw7FjJbWkAZb +cyhD0AYkXKHL/0WLqMfwRwQDwhpi3iNUvJafM/6tunc5BRXMSiGSakYgh/lnCwa1VoY YETUfj7GVa1hCvPLPe8m6+zKuXX3XXOOk1hwq9vioa6d7FJqN1GAnJM8Tj0FoMJRIcvn NPjg== X-Gm-Message-State: ALoCoQljTW51RRRWoHoPJ5BBazIbOeF4MLmjNElSZkVpE37Jm+9e+s8pIq18/vzmDM0McSugs5aK X-Received: by 10.68.98.34 with SMTP id ef2mr48906578pbb.45.1441136131863; Tue, 01 Sep 2015 12:35:31 -0700 (PDT) Received: from localhost.localdomain ([202.62.93.143]) by smtp.gmail.com with ESMTPSA id gw3sm19019035pbc.46.2015.09.01.12.35.29 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 01 Sep 2015 12:35:31 -0700 (PDT) From: Vaibhav Hiremath To: linux-mmc@vger.kernel.org Subject: [RFC 3/3] mmc: sdhci-pxav3: Add ->voltage_switch callback support Date: Wed, 2 Sep 2015 01:02:18 +0530 Message-Id: <1441135938-8056-4-git-send-email-vaibhav.hiremath@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1441135938-8056-1-git-send-email-vaibhav.hiremath@linaro.org> References: <1441135938-8056-1-git-send-email-vaibhav.hiremath@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150901_123552_685242_63DEAADE X-CRM114-Status: GOOD ( 16.75 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ulf.hansson@linaro.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Vaibhav Hiremath MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In case PXA1928 family of devices, there is device/controller specific configuration to control voltage/power on the IO pins. This patch implements and enables the sdhci_ops->voltage_switch() callback api. Note that IO pad register addresses are fetched as a memory resource. For example, in case of PXA1928 and family of devices, the DT property would look something like, sdh1: sdh@d4280000 { compatible = "mrvl,pxav3-mmc"; reg-names = "sdhci", "io-pwr", "io-pwr-lock-unlock"; reg = <0xd4280000 0x120>, <0xd401e81c 4>, <0xd4015068 8>; ... }; Signed-off-by: Vaibhav Hiremath --- drivers/mmc/host/sdhci-pxav3.c | 59 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index 5d26fe0..cebb2f9 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -63,11 +63,18 @@ #define IO_PWR_AKEY_ASSAR 0xeb10 #define IO_PWR_MMC1_PAD_1V8 BIT(2) +/* IO Power control */ +#define IO_PWR_AKEY_ASFAR 0xbaba +#define IO_PWR_AKEY_ASSAR 0xeb10 +#define IO_PWR_MMC1_PAD_1V8 BIT(2) + struct sdhci_pxa { struct clk *clk_core; struct clk *clk_io; u8 power_mode; void __iomem *sdio3_conf_reg; + void __iomem *io_pwr_reg; + void __iomem *io_pwr_lock_reg; }; /* @@ -307,6 +314,38 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) __func__, uhs, ctrl_2); } +static void pxav3_voltage_switch(struct sdhci_host *host, + u8 signal_voltage) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_pxa *pxa = pltfm_host->priv; + unsigned int val; + + if (!pxa->io_pwr_reg || !pxa->io_pwr_lock_reg) + return; + + /* Lock register is 64 bit: First & Second access register */ + writel(IO_PWR_AKEY_ASFAR, pxa->io_pwr_lock_reg); + writel(IO_PWR_AKEY_ASSAR, pxa->io_pwr_lock_reg + 4); + val = readl(pxa->io_pwr_reg); + + switch (signal_voltage) { + case MMC_SIGNAL_VOLTAGE_180: + case MMC_SIGNAL_VOLTAGE_120: + val |= IO_PWR_MMC1_PAD_1V8; + break; + case MMC_SIGNAL_VOLTAGE_330: + default: + val &= ~IO_PWR_MMC1_PAD_1V8; + break; + } + + writel(IO_PWR_AKEY_ASFAR, pxa->io_pwr_lock_reg); + writel(IO_PWR_AKEY_ASSAR, pxa->io_pwr_lock_reg + 4); + + writel(val, pxa->io_pwr_reg); +} + static const struct sdhci_ops pxav3_sdhci_ops = { .set_clock = sdhci_set_clock, .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, @@ -314,6 +353,7 @@ static const struct sdhci_ops pxav3_sdhci_ops = { .set_bus_width = sdhci_set_bus_width, .reset = pxav3_reset, .set_uhs_signaling = pxav3_set_uhs_signaling, + .voltage_switch = pxav3_voltage_switch, }; static struct sdhci_pltfm_data sdhci_pxav3_pdata = { @@ -368,6 +408,7 @@ static int sdhci_pxav3_probe(struct platform_device *pdev) struct sdhci_host *host = NULL; struct sdhci_pxa *pxa = NULL; const struct of_device_id *match; + struct resource *res; int ret; pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL); @@ -408,6 +449,24 @@ static int sdhci_pxav3_probe(struct platform_device *pdev) goto err_mbus_win; } + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "io-pwr-conf"); + if (res) { + pxa->io_pwr_reg = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pxa->io_pwr_reg)) { + ret = PTR_ERR(pxa->io_pwr_reg); + goto err_mbus_win; + } + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "io-pwr-lock-unlock"); + if (res) { + pxa->io_pwr_lock_reg = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pxa->io_pwr_lock_reg)) { + ret = PTR_ERR(pxa->io_pwr_lock_reg); + goto err_mbus_win; + } + } + match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev); if (match) { ret = mmc_of_parse(host->mmc);