From patchwork Fri Sep 4 15:32:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Hiremath X-Patchwork-Id: 7124141 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 26E9A9F1D5 for ; Fri, 4 Sep 2015 15:37:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2360C20840 for ; Fri, 4 Sep 2015 15:37:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2C57C20836 for ; Fri, 4 Sep 2015 15:37:12 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZXt1V-0002b9-CB; Fri, 04 Sep 2015 15:35:29 +0000 Received: from mail-pa0-f46.google.com ([209.85.220.46]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZXt1D-000159-9O for linux-arm-kernel@lists.infradead.org; Fri, 04 Sep 2015 15:35:12 +0000 Received: by pacfv12 with SMTP id fv12so27998856pac.2 for ; Fri, 04 Sep 2015 08:34:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/h6cdCBVOYl3HMS8xDZD648yf/BtB6uz0EkDFCa+0IY=; b=kfxRzGehRhK/whf/iBDt3yOcdL5A6uF5lHd3/FW2zftYj/k+jybOqpxIRadub0W13k 4tXcRxWv/AaP8F70QDNAx7iHp4jAcfmqiVPSn1+0duTGViDEkBfLnEOYYz3MmjMen9Bo v6alRgrFuCese+AwzfJEvEVdkBD70fCcVfqH+8sHdiqcOiWf/jt24PVEVMjTfXncGHzo M0vWyYi/+2jebv0wBSCeLEmPC6lrHmueCxjjLx4tA6tiVR3KIiPeCuYrGOjIi66Po7cb 8W/a8rJs3dSaN1ue2mfTV0vcQj+Hyv5GhPcCd+Zg4RTZ3fmsXoXBNP/8p2HE5oiYDxaA d01Q== X-Gm-Message-State: ALoCoQndIdpx4rEBfsP4qeR4eljtGFHoA3kbFSz0k83SgTBGMiS5xsncd0V0XyHrZN6P6kimIf/k X-Received: by 10.68.241.103 with SMTP id wh7mr9493871pbc.88.1441380894121; Fri, 04 Sep 2015 08:34:54 -0700 (PDT) Received: from localhost.localdomain ([202.62.93.137]) by smtp.gmail.com with ESMTPSA id gs2sm2920151pbc.15.2015.09.04.08.34.50 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 04 Sep 2015 08:34:53 -0700 (PDT) From: Vaibhav Hiremath To: linux-mmc@vger.kernel.org Subject: [PATCH 3/5] mmc: sdhci-pxav3: Add pinctl setting according to bus clock Date: Fri, 4 Sep 2015 21:02:19 +0530 Message-Id: <1441380741-13115-4-git-send-email-vaibhav.hiremath@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1441380741-13115-1-git-send-email-vaibhav.hiremath@linaro.org> References: <1441380741-13115-1-git-send-email-vaibhav.hiremath@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150904_083511_496305_5F69DAF9 X-CRM114-Status: GOOD ( 15.94 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vaibhav Hiremath , ulf.hansson@linaro.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kliu5@marvell.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Different bus clock may need different pin setting. For example, fast bus clock like 208Mhz need pin drive fast while slow bus clock prefer pin drive slow to guarantee signal quality. So this patch creates two states, - Default (slow/normal) pin state - And fast pin state for higher freq bus speed. And selection of pin state is done based on timing mode. Signed-off-by: Vaibhav Hiremath Signed-off-by: Kevin Liu --- drivers/mmc/host/sdhci-pxav3.c | 45 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index c2b2b78..d933f75 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "sdhci.h" #include "sdhci-pltfm.h" @@ -92,6 +93,10 @@ struct sdhci_pxa { void __iomem *io_pwr_reg; void __iomem *io_pwr_lock_reg; struct sdhci_pxa_data *data; + + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_fast; }; static struct sdhci_pxa_data pxav3_data_v1 = { @@ -298,6 +303,33 @@ static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode) pxa->power_mode = power_mode; } +static int pxav3_select_pinstate(struct sdhci_host *host, unsigned int uhs) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_pxa *pxa = pltfm_host->priv; + struct pinctrl_state *pinctrl; + + if (IS_ERR(pxa->pinctrl) || + IS_ERR(pxa->pins_default) || + IS_ERR(pxa->pins_fast)) + return -EINVAL; + + switch (uhs) { + case MMC_TIMING_UHS_SDR50: + case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_MMC_HS200: + case MMC_TIMING_MMC_HS400: + pinctrl = pxa->pins_fast; + break; + default: + /* back to default state for other legacy timing */ + pinctrl = pxa->pins_default; + break; + } + + return pinctrl_select_state(pxa->pinctrl, pinctrl); +} + static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -353,6 +385,8 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) dev_dbg(mmc_dev(host->mmc), "%s uhs = %d, ctrl_2 = %04X\n", __func__, uhs, ctrl_2); + + pxav3_select_pinstate(host, uhs); } static void pxav3_voltage_switch(struct sdhci_host *host, @@ -416,7 +450,6 @@ static void pxav3_set_clock(struct sdhci_host *host, unsigned int clock) /* TX internal clock selection */ pxav3_set_tx_clock(host); } - } static const struct sdhci_ops pxav3_sdhci_ops = { @@ -586,6 +619,16 @@ static int sdhci_pxav3_probe(struct platform_device *pdev) } } + pxa->pinctrl = devm_pinctrl_get(dev); + if (!IS_ERR(pxa->pinctrl)) { + pxa->pins_default = pinctrl_lookup_state(pxa->pinctrl, "default"); + if (IS_ERR(pxa->pins_default)) + dev_err(dev, "could not get default pinstate\n"); + pxa->pins_fast = pinctrl_lookup_state(pxa->pinctrl, "fast"); + if (IS_ERR(pxa->pins_fast)) + dev_info(dev, "could not get fast pinstate\n"); + } + pm_runtime_get_noresume(&pdev->dev); pm_runtime_set_active(&pdev->dev); pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);