From patchwork Fri Sep 4 15:32:20 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Hiremath X-Patchwork-Id: 7124151 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C4E8EBEEC1 for ; Fri, 4 Sep 2015 15:37:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F413320842 for ; Fri, 4 Sep 2015 15:37:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AB5DB2083E for ; Fri, 4 Sep 2015 15:37:12 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZXt1d-0002iD-GB; Fri, 04 Sep 2015 15:35:37 +0000 Received: from mail-pa0-f50.google.com ([209.85.220.50]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZXt1K-0001Au-KQ for linux-arm-kernel@lists.infradead.org; Fri, 04 Sep 2015 15:35:19 +0000 Received: by pacfv12 with SMTP id fv12so28000369pac.2 for ; Fri, 04 Sep 2015 08:34:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ncPiABK2SoHkaRTxpAws9yzhyA2/cmfPePE+RDYvcjY=; b=T+NAppu3QilZj0GsWQ3/Z86XR1DZI7A0EN/IqKzsJ1f5GI/jtJlxWXiKdPQdUioHPu Mepcs+m6zR2bmk7pG+GwSN4/IdBqLrIk9h/X4t3Qd8QnGcEhm46v95+00UfyzNcvKnrJ 1zjeY4rePdSdtkZ21iHw1KRN2h7Md2owTwhTrGnnQBYUPGapUG5kcUw0xePUtkYED2td PhoASFgMoMzB/gVkmVHgTqBJJMfZBkyp+gSJSd2ChcjF4LsGbxuAHIE0eCFGP9sN8pM8 m+ECsstfO/NzejOWGhDaHt/TAWauHBwEDMfWw1+CUq+XVgVXcfbIq5otR2yf02aAFrxA KWwA== X-Gm-Message-State: ALoCoQm1j3qGeyMWlWdhbqrdHChJ50/knlaY5yat8+y4b5pCymsZJONaydZRXPcp/qihpX7yPSRR X-Received: by 10.68.96.197 with SMTP id du5mr9548519pbb.32.1441380897832; Fri, 04 Sep 2015 08:34:57 -0700 (PDT) Received: from localhost.localdomain ([202.62.93.137]) by smtp.gmail.com with ESMTPSA id gs2sm2920151pbc.15.2015.09.04.08.34.54 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 04 Sep 2015 08:34:57 -0700 (PDT) From: Vaibhav Hiremath To: linux-mmc@vger.kernel.org Subject: [PATCH 4/5] mmc: sdhci-pxav3: Fix HS200 mode support Date: Fri, 4 Sep 2015 21:02:20 +0530 Message-Id: <1441380741-13115-5-git-send-email-vaibhav.hiremath@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1441380741-13115-1-git-send-email-vaibhav.hiremath@linaro.org> References: <1441380741-13115-1-git-send-email-vaibhav.hiremath@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150904_083518_737471_396BECF3 X-CRM114-Status: GOOD ( 15.32 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ulf.hansson@linaro.org, Tim Wang , Vaibhav Hiremath , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kliu5@marvell.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Kevin Liu IN case of MMC HS200 mode, current code does not enable SD_CE_ATA_2.MMC_HS200 & SD_CE_ATA_2.MMC_CARD bit configurations. So this patch updates the above bit fields correctly. Signed-off-by: Tim Wang Signed-off-by: Kevin Liu Signed-off-by: Vaibhav Hiremath --- Note: Unfortunately I do not have access to any other datasheets which uses sdhci-pxav3 driver, so quite not sure whether this would break any existing platform, probably NOT, as I do not see any references for this change. If anyone can confirm that would be really great. drivers/mmc/host/sdhci-pxav3.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index d933f75..6978810 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -57,6 +57,8 @@ #define SD_CE_ATA_1 0x10C #define SD_CE_ATA_2 0x10E +#define SD_CE_ATA2_HS200_EN BIT(10) +#define SD_CE_ATA2_MMC_MODE BIT(12) #define SDCE_MISC_INT BIT(2) #define SDCE_MISC_INT_EN BIT(1) @@ -330,6 +332,17 @@ static int pxav3_select_pinstate(struct sdhci_host *host, unsigned int uhs) return pinctrl_select_state(pxa->pinctrl, pinctrl); } +static int pxav3_select_hs200(struct sdhci_host *host) +{ + u16 reg = 0; + + reg = sdhci_readw(host, SD_CE_ATA_2); + reg |= SD_CE_ATA2_HS200_EN | SD_CE_ATA2_MMC_MODE; + sdhci_writew(host, reg, SD_CE_ATA_2); + + return 0; +} + static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -361,6 +374,10 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) case MMC_TIMING_UHS_DDR50: ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180; break; + case MMC_TIMING_MMC_HS200: + ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180; + pxav3_select_hs200(host); + break; } /*