From patchwork Fri Sep 4 16:04:11 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yury Norov X-Patchwork-Id: 7124331 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A39CF9F695 for ; Fri, 4 Sep 2015 16:08:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BC795208B2 for ; Fri, 4 Sep 2015 16:08:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 75DDD2089F for ; Fri, 4 Sep 2015 16:08:32 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZXtVd-0000mG-2h; Fri, 04 Sep 2015 16:06:37 +0000 Received: from mail-bn1on0070.outbound.protection.outlook.com ([157.56.110.70] helo=na01-bn1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZXtVa-0006W2-8m for linux-arm-kernel@lists.infradead.org; Fri, 04 Sep 2015 16:06:35 +0000 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Yuri.Norov@caviumnetworks.com; Received: from localhost (91.77.150.194) by DM2PR07MB622.namprd07.prod.outlook.com (10.141.177.146) with Microsoft SMTP Server (TLS) id 15.1.256.15; Fri, 4 Sep 2015 16:04:34 +0000 From: Yury Norov To: , , Subject: [RFC PATCH] arm64: cpuinfo: reduce cache contention on update_{feature}_support Date: Fri, 4 Sep 2015 19:04:11 +0300 Message-ID: <1441382651-12058-1-git-send-email-ynorov@caviumnetworks.com> X-Mailer: git-send-email 2.1.4 MIME-Version: 1.0 X-Originating-IP: [91.77.150.194] X-ClientProxiedBy: HE1PR01CA0012.eurprd01.prod.exchangelabs.com (25.163.2.150) To DM2PR07MB622.namprd07.prod.outlook.com (10.141.177.146) X-Microsoft-Exchange-Diagnostics: 1; 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DM2PR07MB622; 5:vq+GPTWWl7tmU40nd34OkdlUSOVSE1zXydxKIo6WSjmBfKKB6fkEGJ8ZuKDpfKpKamSH4sQe6BpdvQxHjIYbLKtcwfe8U099P7vdJQC0Qfhn1uBRGx3rKpLlIm7OfXRY0TH8+G0TQ52HmFG30Vd0RA==; 24:1LnpNbJYC8FyvJryRIa+VuZTKctskrOAfNP+DEcmSRlT2/7sRG4CZyAQ7QB2Q8zlpSOd3MnUK40DzXv6q61LOj7duIEbP9aYUrRHAVEELSc=; 20:621IUM96bPsaOyjDbMCVQ+jvm4weCGh3vKzYg6Ok47QtDbtfyVLdUhslMHV2p4+c9BHRb4n6cLwcXaNMYalTfw== SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2015 16:04:34.9840 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR07MB622 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150904_090634_529799_5DA348CB X-CRM114-Status: GOOD ( 10.03 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yury.norov@gmail.com, Suzuki.Poulose@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, klimov.linux@gmail.com, Yury Norov , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAD_ENC_HEADER,BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch is on top of https://lkml.org/lkml/2015/9/2/413 In master, there's only a single function - update_mixed_endian_el0_support And similar function is on review mentioned above. The algorithm for them is like this: - there's system-wide boolean marker for the feature that is initially enabled; - there's also updater for the feature that may disable it system-widely if feature is not supported on current CPU. - updater is called for each CPU on bootup. The problem is the way updater does its work. On each CPU, it unconditionally updates system-wide marker. For multi-core system it makes CPU issue invalidate message for a cache line containing marker. This invalidate increases cache contention for nothing, because there's a single marker reset that is really needed, and the others are useless. If the number of system-wide markers of this sort will grow, it may become a trouble on large-scale SOCs. The fix is trivial, though: do system-wide marker update conditionally, and preserve corresponding cache line in shared state for all update() calls, except, probably, one. Signed-off-by: Yury Norov --- arch/arm64/kernel/cpuinfo.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 4a6ae31..9972c1e 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -87,12 +87,14 @@ bool system_supports_aarch32_el0(void) static void update_mixed_endian_el0_support(struct cpuinfo_arm64 *info) { - mixed_endian_el0 &= id_aa64mmfr0_mixed_endian_el0(info->reg_id_aa64mmfr0); + if (mixed_endian_el0 && !id_aa64mmfr0_mixed_endian_el0(info->reg_id_aa64mmfr0)) + mixed_endian_el0 = false; } static void update_aarch32_el0_support(struct cpuinfo_arm64 *info) { - aarch32_el0 &= id_aa64pfr0_aarch32_el0(info->reg_id_aa64pfr0); + if (aarch32_el0 && !id_aa64pfr0_aarch32_el0(info->reg_id_aa64pfr0)) + aarch32_el0 = false; } static void update_cpu_features(struct cpuinfo_arm64 *info)