From patchwork Mon Sep 7 11:18:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Hiremath X-Patchwork-Id: 7133711 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 289FC9F314 for ; Mon, 7 Sep 2015 11:24:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 464652041B for ; Mon, 7 Sep 2015 11:23:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4C8A420680 for ; Mon, 7 Sep 2015 11:23:58 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZYuUe-0003CK-L6; Mon, 07 Sep 2015 11:21:48 +0000 Received: from mail-pa0-f42.google.com ([209.85.220.42]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZYuUP-00033E-2t for linux-arm-kernel@lists.infradead.org; Mon, 07 Sep 2015 11:21:34 +0000 Received: by pacfv12 with SMTP id fv12so97085259pac.2 for ; Mon, 07 Sep 2015 04:21:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uc73q+KGFzx0kwX9ZnXEnZex57kcoHZkGT5HXWoxtV8=; b=NASZqKzxbV3gvDFfeKvWULK1utdsFxCd9Qa58qnubzaZdqxxrKTndiDPy3eOTLgKQ7 9HdRBW2pJQfwUVZrdHLpwNrQUdDWjzHKGHTGLvdEQ/oUXXnR0Bkfx1wK3onmI1EXGYRW /IQqVH0dDLjNkTQK02cP1D/I6wh3o450EojkHQYjItmtBs1wvLkpGdsT+Td3H865sD97 poy2p53ryOOPWNcJqpl+x+sS2EZGpPXyT/Y++m7Dw19WXR78GpVoJLjozyOQocUBTivh uX1ZD9tIpmMsaZDucjsooNN3LkxvjxVSXUl0sw2UTyf+EakvNsNUtvJouOTp1nG71FZ+ eGzw== X-Gm-Message-State: ALoCoQl7tfNWJk03fP8fUznUEPH/erXgs1/EwgWE69qkE+rv2YANJ04aGj3tV8pJ0wA3Kq9X83er X-Received: by 10.66.159.197 with SMTP id xe5mr45239262pab.32.1441624871904; Mon, 07 Sep 2015 04:21:11 -0700 (PDT) Received: from localhost.localdomain ([202.62.93.139]) by smtp.gmail.com with ESMTPSA id fm5sm11654737pbb.60.2015.09.07.04.21.08 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Sep 2015 04:21:10 -0700 (PDT) From: Vaibhav Hiremath To: linux-mmc@vger.kernel.org Subject: [PATCH-v2 3/7] mmc: sdhci-pxav3: Add platform specific set_clock ops Date: Mon, 7 Sep 2015 16:48:37 +0530 Message-Id: <1441624721-15612-4-git-send-email-vaibhav.hiremath@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1441624721-15612-1-git-send-email-vaibhav.hiremath@linaro.org> References: <1441624721-15612-1-git-send-email-vaibhav.hiremath@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150907_042133_179958_F5792A44 X-CRM114-Status: GOOD ( 16.97 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, ulf.hansson@linaro.org, linux-kernel@vger.kernel.org, Vaibhav Hiremath , robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In case of PXA1928 & family of devices, the TX BUS and internal clock need to be set as part of ->set_clock() ops, so this patch adds platform specific ->set_clock() operation. Note that, in order to not break other platforms, this patch introduced the flag, which controls whether controller/platform specific clock configuration needs to be executed. Signed-off-by: Vaibhav Hiremath --- drivers/mmc/host/sdhci-pxav3.c | 46 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index aecae04..c2b2b78 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -48,6 +48,10 @@ #define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF #define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24 +#define SD_FIFO_PARAM 0x104 +#define INTERNAL_CLK_GATE_CTRL BIT(8) +#define INTERNAL_CLK_GATE_ON BIT(9) + #define SD_SPI_MODE 0x108 #define SD_CE_ATA_1 0x10C @@ -57,6 +61,9 @@ #define SD_RX_CFG_REG 0x114 +#define TX_CFG_REG 0x118 +#define TX_INTERNAL_SEL_BUS_CLK BIT(30) + /* IO Power control */ #define IO_PWR_AKEY_ASFAR 0xbaba #define IO_PWR_AKEY_ASSAR 0xeb10 @@ -68,6 +75,9 @@ struct sdhci_pxa_data { u8 sdclk_delay_shift; u8 sdclk_sel_mask; u8 sdclk_sel_shift; + + /* set this if platform needs separate clock configuration */ + bool set_pltfrm_clk; /* * We have few more differences, add them along with their * respective feature support @@ -90,6 +100,7 @@ static struct sdhci_pxa_data pxav3_data_v1 = { .sdclk_delay_shift = 9, .sdclk_sel_mask = 0x1, .sdclk_sel_shift = 8, + .set_pltfrm_clk = false, }; static struct sdhci_pxa_data pxav3_data_v2 = { @@ -99,6 +110,7 @@ static struct sdhci_pxa_data pxav3_data_v2 = { /* Only set SDCLK_SEL1, as driver uses default value of SDCLK_SEL0 */ .sdclk_sel_mask = 0x3, .sdclk_sel_shift = 2, /* SDCLK_SEL1 */ + .set_pltfrm_clk = true, }; /* @@ -375,8 +387,40 @@ static void pxav3_voltage_switch(struct sdhci_host *host, writel(val, pxa->io_pwr_reg); } +static void pxav3_set_tx_clock(struct sdhci_host *host) +{ + u32 val; + + val = sdhci_readl(host, TX_CFG_REG); + val |= TX_INTERNAL_SEL_BUS_CLK; + sdhci_writel(host, val, TX_CFG_REG); +} + +static void pxav3_set_clock(struct sdhci_host *host, unsigned int clock) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_pxa *pxa = pltfm_host->priv; + + /* We still use common sdhci_set_clock() */ + sdhci_set_clock(host, clock); + + /* platform/controller specific clock configuration */ + if (pxa->data->set_pltfrm_clk && clock != 0) { + u32 val; + + val = sdhci_readw(host, SD_FIFO_PARAM); + /* Internal clock gate ON and CTRL = 0b11 */ + val |= INTERNAL_CLK_GATE_CTRL | INTERNAL_CLK_GATE_ON; + sdhci_writew(host, val, SD_FIFO_PARAM); + + /* TX internal clock selection */ + pxav3_set_tx_clock(host); + } + +} + static const struct sdhci_ops pxav3_sdhci_ops = { - .set_clock = sdhci_set_clock, + .set_clock = pxav3_set_clock, .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, .get_max_clock = sdhci_pltfm_clk_get_max_clock, .set_bus_width = sdhci_set_bus_width,