From patchwork Mon Sep 7 11:18:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Hiremath X-Patchwork-Id: 7133721 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8E7EFBEEC1 for ; Mon, 7 Sep 2015 11:24:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A93BA20681 for ; Mon, 7 Sep 2015 11:24:08 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C4BA220680 for ; Mon, 7 Sep 2015 11:24:07 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZYuUm-0003HU-Q4; Mon, 07 Sep 2015 11:21:56 +0000 Received: from mail-pa0-f52.google.com ([209.85.220.52]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZYuUS-00033O-ST for linux-arm-kernel@lists.infradead.org; Mon, 07 Sep 2015 11:21:38 +0000 Received: by padhk3 with SMTP id hk3so10021764pad.3 for ; Mon, 07 Sep 2015 04:21:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/h6cdCBVOYl3HMS8xDZD648yf/BtB6uz0EkDFCa+0IY=; b=Wc6hkgcuYJOGkp6UL5PHqsUQpv1SH6wB9f+MjMH+oyxpmbFvRqJL9mgcyrk9uECOo1 rPRrgSquAEj/rzzON0cbGXReN2WhkR79iqy3UpnwQ6zy8Jdql+rcRJXG4f6Pg6TwHRmo j+9fIljeG0w/7mKzgdwHi/8xDkXghAduAYvSTSGfSvCz3Mb6dgkwVrOEdiMoHghjAhoV i0jox4U7ZleTUssNEDuZekGtapzXslB1ZLIRqlMXuQEbm9zsTQwNJ0/39ocFS2yKCkOb WZdIJnxUA1JI7qdhV2AMt06mkeHrtRlYeEVgiOOWrAGCp6ytOFyTiENXhXTvCmglWFZ1 wuAg== X-Gm-Message-State: ALoCoQnz2257f6LYE+Sc0F+n3eecUBGccCr5l1lxuCVjiFFBsNiYzr7JHHXpPVDj2DlFP5lUksem X-Received: by 10.68.226.134 with SMTP id rs6mr44939345pbc.11.1441624875811; Mon, 07 Sep 2015 04:21:15 -0700 (PDT) Received: from localhost.localdomain ([202.62.93.139]) by smtp.gmail.com with ESMTPSA id fm5sm11654737pbb.60.2015.09.07.04.21.12 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Sep 2015 04:21:14 -0700 (PDT) From: Vaibhav Hiremath To: linux-mmc@vger.kernel.org Subject: [PATCH-v2 4/7] mmc: sdhci-pxav3: Add pinctl setting according to bus clock Date: Mon, 7 Sep 2015 16:48:38 +0530 Message-Id: <1441624721-15612-5-git-send-email-vaibhav.hiremath@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1441624721-15612-1-git-send-email-vaibhav.hiremath@linaro.org> References: <1441624721-15612-1-git-send-email-vaibhav.hiremath@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150907_042137_042080_F0FA271C X-CRM114-Status: GOOD ( 15.71 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, ulf.hansson@linaro.org, linux-kernel@vger.kernel.org, Vaibhav Hiremath , robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, Kevin Liu MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Different bus clock may need different pin setting. For example, fast bus clock like 208Mhz need pin drive fast while slow bus clock prefer pin drive slow to guarantee signal quality. So this patch creates two states, - Default (slow/normal) pin state - And fast pin state for higher freq bus speed. And selection of pin state is done based on timing mode. Signed-off-by: Vaibhav Hiremath Signed-off-by: Kevin Liu Reviewed-by: Linus Walleij --- drivers/mmc/host/sdhci-pxav3.c | 45 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index c2b2b78..d933f75 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "sdhci.h" #include "sdhci-pltfm.h" @@ -92,6 +93,10 @@ struct sdhci_pxa { void __iomem *io_pwr_reg; void __iomem *io_pwr_lock_reg; struct sdhci_pxa_data *data; + + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_fast; }; static struct sdhci_pxa_data pxav3_data_v1 = { @@ -298,6 +303,33 @@ static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode) pxa->power_mode = power_mode; } +static int pxav3_select_pinstate(struct sdhci_host *host, unsigned int uhs) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_pxa *pxa = pltfm_host->priv; + struct pinctrl_state *pinctrl; + + if (IS_ERR(pxa->pinctrl) || + IS_ERR(pxa->pins_default) || + IS_ERR(pxa->pins_fast)) + return -EINVAL; + + switch (uhs) { + case MMC_TIMING_UHS_SDR50: + case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_MMC_HS200: + case MMC_TIMING_MMC_HS400: + pinctrl = pxa->pins_fast; + break; + default: + /* back to default state for other legacy timing */ + pinctrl = pxa->pins_default; + break; + } + + return pinctrl_select_state(pxa->pinctrl, pinctrl); +} + static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -353,6 +385,8 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) dev_dbg(mmc_dev(host->mmc), "%s uhs = %d, ctrl_2 = %04X\n", __func__, uhs, ctrl_2); + + pxav3_select_pinstate(host, uhs); } static void pxav3_voltage_switch(struct sdhci_host *host, @@ -416,7 +450,6 @@ static void pxav3_set_clock(struct sdhci_host *host, unsigned int clock) /* TX internal clock selection */ pxav3_set_tx_clock(host); } - } static const struct sdhci_ops pxav3_sdhci_ops = { @@ -586,6 +619,16 @@ static int sdhci_pxav3_probe(struct platform_device *pdev) } } + pxa->pinctrl = devm_pinctrl_get(dev); + if (!IS_ERR(pxa->pinctrl)) { + pxa->pins_default = pinctrl_lookup_state(pxa->pinctrl, "default"); + if (IS_ERR(pxa->pins_default)) + dev_err(dev, "could not get default pinstate\n"); + pxa->pins_fast = pinctrl_lookup_state(pxa->pinctrl, "fast"); + if (IS_ERR(pxa->pins_fast)) + dev_info(dev, "could not get fast pinstate\n"); + } + pm_runtime_get_noresume(&pdev->dev); pm_runtime_set_active(&pdev->dev); pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);