From patchwork Mon Sep 14 13:26:21 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 7176121 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7B0279F336 for ; Mon, 14 Sep 2015 13:31:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 51BEB205B9 for ; Mon, 14 Sep 2015 13:31:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 97A6B2064F for ; Mon, 14 Sep 2015 13:30:58 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZbToo-0001j8-1l; Mon, 14 Sep 2015 13:29:14 +0000 Received: from merlin.infradead.org ([2001:4978:20e::2]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZbToM-0001JT-3U for linux-arm-kernel@bombadil.infradead.org; Mon, 14 Sep 2015 13:28:46 +0000 Received: from mail-wi0-f169.google.com ([209.85.212.169]) by merlin.infradead.org with esmtps (Exim 4.85 #2 (Red Hat Linux)) id 1ZbToK-0002y6-KX for linux-arm-kernel@lists.infradead.org; Mon, 14 Sep 2015 13:28:45 +0000 Received: by wicge5 with SMTP id ge5so142859396wic.0 for ; Mon, 14 Sep 2015 06:28:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bklXAJEaFg4BscdCPQo3d7xiYKgnTnJnxa0i8vAGPTI=; b=NSggsFL6vVilAcrnR5KA3NaM8/mLAJ6h6ZNOEIrS6/UEJoEMc3thNowMUi71Xv4+Pq edUfiOZlJ7Zlux7yxmPpyalyWw/yVJ/VgzFop89C4aVz9jkUYpCM4s4XxCmi6bdXLJw/ z+fMpsMP5jef/BxhdYnR2/2DMWaJHHKVdZpvMQ8RyEDDbw+gA24P9ULQ6Q7Zikqe5Jpy W/iztum+BZpMUHKOUwhGOY55WoXiGtOmp6WWh85mvsMh9Bthjrx130a6eAQAib9DElQu AdtE2OIo1IFeBYoZHb04dgfxqDV8vkfOrsNmQ2fyGeGnzzQGNB3nB07LVlht9jIGZk1v gHBQ== X-Gm-Message-State: ALoCoQl9S4t9tjc6FyW3PEB8IbeXf/LnYw7pyd+BB0DD63HFuEuG3OgK6U1yRs2HQZbZE+lKoa+k X-Received: by 10.180.84.99 with SMTP id x3mr26496897wiy.16.1442237297679; Mon, 14 Sep 2015 06:28:17 -0700 (PDT) Received: from wychelm.lan (cpc4-aztw19-0-0-cust71.18-1.cable.virginm.net. [82.33.25.72]) by smtp.gmail.com with ESMTPSA id ht5sm14415869wib.10.2015.09.14.06.28.16 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Sep 2015 06:28:17 -0700 (PDT) From: Daniel Thompson To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH v2 7/7] arm64: irqflags: Automatically identify I bit mis-management Date: Mon, 14 Sep 2015 14:26:21 +0100 Message-Id: <1442237181-17064-8-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1442237181-17064-1-git-send-email-daniel.thompson@linaro.org> References: <1442237181-17064-1-git-send-email-daniel.thompson@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150914_092844_797173_F23E7903 X-CRM114-Status: GOOD ( 16.57 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Thompson , linaro-kernel@lists.linaro.org, patches@linaro.org, Marc Zyngier , Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org, Dave Martin , John Stultz , Andrew Thoelke , Sumit Semwal MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This is self-test code to identify circumstances where the I bit is set by hardware but no software exists to copy its state to the PMR. I don't really expect this patch to be retained much after the RFC stage. However I have included it in this RFC series to document the testing I have done and to allow further testing under different workloads. Signed-off-by: Daniel Thompson --- arch/arm64/include/asm/irqflags.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h index cf8a5184fce7..b2998b7946b6 100644 --- a/arch/arm64/include/asm/irqflags.h +++ b/arch/arm64/include/asm/irqflags.h @@ -19,8 +19,10 @@ #ifdef __KERNEL__ #include +#include #include +#include #include #include @@ -94,6 +96,33 @@ static inline void maybe_switch_to_sysreg_gic_cpuif(void) {} #else /* CONFIG_IRQFLAGS_GIC_MASKING */ +static inline void check_for_i_bit(void) +{ +#ifdef CONFIG_USE_ICC_SYSREGS_FOR_IRQFLAGS + unsigned long flags; + + /* check whether the I-bit is spuriously enabled */ + if (!in_nmi()) { + asm volatile(ALTERNATIVE( + "mov %0, #0", + "mrs %0, daif", + ARM64_HAS_SYSREG_GIC_CPUIF) + : "=r" (flags)); + + WARN_ONCE(flags & PSR_I_BIT, "I bit is set: %08lx\n", flags); + } + + /* check that the PMR has a legal value */ + asm volatile(ALTERNATIVE( + "mov %0, #" __stringify(ICC_PMR_EL1_MASKED), + "mrs_s %0, " __stringify(ICC_PMR_EL1), + ARM64_HAS_SYSREG_GIC_CPUIF) + : "=r" (flags)); + WARN_ONCE((flags & ICC_PMR_EL1_MASKED) != ICC_PMR_EL1_MASKED, + "ICC_PMR_EL1 has a bad value: %08lx\n", flags); +#endif +} + /* * CPU interrupt mask handling. */ @@ -101,6 +130,7 @@ static inline unsigned long arch_local_irq_save(void) { unsigned long flags, masked = ICC_PMR_EL1_MASKED; + check_for_i_bit(); asm volatile(ALTERNATIVE( "mrs %0, daif // arch_local_irq_save\n" "msr daifset, #2", @@ -119,6 +149,7 @@ static inline void arch_local_irq_enable(void) { unsigned long unmasked = ICC_PMR_EL1_UNMASKED; + check_for_i_bit(); asm volatile(ALTERNATIVE( "msr daifclr, #2 // arch_local_irq_enable", "msr_s " __stringify(ICC_PMR_EL1) ",%0", @@ -132,6 +163,7 @@ static inline void arch_local_irq_disable(void) { unsigned long masked = ICC_PMR_EL1_MASKED; + check_for_i_bit(); asm volatile(ALTERNATIVE( "msr daifset, #2 // arch_local_irq_disable", "msr_s " __stringify(ICC_PMR_EL1) ",%0", @@ -148,6 +180,7 @@ static inline unsigned long arch_local_save_flags(void) { unsigned long flags; + check_for_i_bit(); asm volatile(ALTERNATIVE( "mrs %0, daif // arch_local_save_flags", "mrs_s %0, " __stringify(ICC_PMR_EL1), @@ -164,6 +197,7 @@ static inline unsigned long arch_local_save_flags(void) */ static inline void arch_local_irq_restore(unsigned long flags) { + check_for_i_bit(); asm volatile(ALTERNATIVE( "msr daif, %0 // arch_local_irq_restore", "msr_s " __stringify(ICC_PMR_EL1) ",%0", @@ -175,6 +209,7 @@ static inline void arch_local_irq_restore(unsigned long flags) static inline int arch_irqs_disabled_flags(unsigned long flags) { + check_for_i_bit(); asm volatile(ALTERNATIVE( "and %0, %0, #" __stringify(PSR_I_BIT) "\n" "nop",