From patchwork Tue Sep 15 15:41:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 7187411 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C7473BEEC1 for ; Tue, 15 Sep 2015 15:46:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E1416204D9 for ; Tue, 15 Sep 2015 15:46:23 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 164112054E for ; Tue, 15 Sep 2015 15:46:23 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZbsPG-0001Nq-2c; Tue, 15 Sep 2015 15:44:30 +0000 Received: from eu-smtp-delivery-143.mimecast.com ([207.82.80.143]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZbsP9-0000Zz-VA for linux-arm-kernel@lists.infradead.org; Tue, 15 Sep 2015 15:44:26 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-33-UPpkAnsmSxqRUYV0bP-d8g-9; Tue, 15 Sep 2015 16:41:43 +0100 Received: from e106634-lin.cambridge.arm.com ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 15 Sep 2015 16:41:41 +0100 From: "Suzuki K. Poulose" To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 10/15] arm64: kvm: Fix {V}TCR_EL2_TG0 mask Date: Tue, 15 Sep 2015 16:41:19 +0100 Message-Id: <1442331684-28818-11-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1442331684-28818-1-git-send-email-suzuki.poulose@arm.com> References: <1442331684-28818-1-git-send-email-suzuki.poulose@arm.com> X-OriginalArrivalTime: 15 Sep 2015 15:41:41.0062 (UTC) FILETIME=[04251E60:01D0EFCD] X-MC-Unique: UPpkAnsmSxqRUYV0bP-d8g-9 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150915_084424_458839_3E0B2D57 X-CRM114-Status: UNSURE ( 7.45 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -4.2 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark.Rutland@arm.com, kvm@vger.kernel.org, ard.biesheuvel@linaro.org, Marc Zyngier , Catalin Marinas , suzuki.poulose@arm.com, Will Deacon , linux-kernel@vger.kernel.org, kvmarm@lists.cs.columbia.edu, Christoffer Dall MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Suzuki K. Poulose" {V}TCR_EL2_TG0 is a 2bit wide field, where: 00 - 4K 01 - 64K 10 - 16K But we use only 1 bit, which has worked well so far since we never cared about 16K. Fix it for 16K support. Cc: Catalin Marinas Cc: Will Deacon Cc: Marc Zyngier Cc: Christoffer Dall Cc: kvmarm@lists.cs.columbia.edu Acked-by: Mark Rutland Signed-off-by: Suzuki K. Poulose Reviewed-by: Christoffer Dall --- arch/arm64/include/asm/kvm_arm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 7605e09..bdf139e 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -98,7 +98,7 @@ #define TCR_EL2_TBI (1 << 20) #define TCR_EL2_PS (7 << 16) #define TCR_EL2_PS_40B (2 << 16) -#define TCR_EL2_TG0 (1 << 14) +#define TCR_EL2_TG0 (3 << 14) #define TCR_EL2_SH0 (3 << 12) #define TCR_EL2_ORGN0 (3 << 10) #define TCR_EL2_IRGN0 (3 << 8) @@ -110,7 +110,7 @@ /* VTCR_EL2 Registers bits */ #define VTCR_EL2_PS_MASK (7 << 16) -#define VTCR_EL2_TG0_MASK (1 << 14) +#define VTCR_EL2_TG0_MASK (3 << 14) #define VTCR_EL2_TG0_4K (0 << 14) #define VTCR_EL2_TG0_64K (1 << 14) #define VTCR_EL2_SH0_MASK (3 << 12)