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[1/4] ARM: dts: sun8i: Add PWM controller node for A23/A33

Message ID 1442561739-6824-2-git-send-email-wens@csie.org (mailing list archive)
State New, archived
Headers show

Commit Message

Chen-Yu Tsai Sept. 18, 2015, 7:35 a.m. UTC 
A23/A33 have a PWM controller that is compatible to the one on the A20.
Add a device node for it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Hans de Goede Sept. 18, 2015, 3:29 p.m. UTC | #1 
Hi,

Good stuff, thanks for working on this.

On 09/18/2015 03:35 AM, Chen-Yu Tsai wrote:
> A23/A33 have a PWM controller that is compatible to the one on the A20.
> Add a device node for it.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Looks good to me:

Reviewed-by: Hans de Goede <hdegoede@redhat.com>

Regards,

Hans


> ---
>   arch/arm/boot/dts/sun8i-a23-a33.dtsi | 8 ++++++++
>   1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> index 27a925ec17d2..e7054304018a 100644
> --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> @@ -466,6 +466,14 @@
>   			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>   		};
>
> +		pwm: pwm@01c21400 {
> +			compatible = "allwinner,sun7i-a20-pwm";
> +			reg = <0x01c21400 0xc>;
> +			clocks = <&osc24M>;
> +			#pwm-cells = <3>;
> +			status = "disabled";
> +		};
> +
>   		lradc: lradc@01c22800 {
>   			compatible = "allwinner,sun4i-a10-lradc-keys";
>   			reg = <0x01c22800 0x100>;
>
Maxime Ripard Sept. 18, 2015, 7:24 p.m. UTC | #2 
On Fri, Sep 18, 2015 at 03:35:36PM +0800, Chen-Yu Tsai wrote:
> A23/A33 have a PWM controller that is compatible to the one on the A20.
> Add a device node for it.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!
Maxime
diff mbox

Patch

diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 27a925ec17d2..e7054304018a 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -466,6 +466,14 @@ 
 			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		pwm: pwm@01c21400 {
+			compatible = "allwinner,sun7i-a20-pwm";
+			reg = <0x01c21400 0xc>;
+			clocks = <&osc24M>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		lradc: lradc@01c22800 {
 			compatible = "allwinner,sun4i-a10-lradc-keys";
 			reg = <0x01c22800 0x100>;