From patchwork Tue Sep 29 02:13:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhengxing X-Patchwork-Id: 7282081 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2C86BBEEA4 for ; Tue, 29 Sep 2015 02:18:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 41EFD206E2 for ; Tue, 29 Sep 2015 02:18:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 48F3A2069A for ; Tue, 29 Sep 2015 02:18:10 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZgkS8-0003aW-9q; Tue, 29 Sep 2015 02:15:36 +0000 Received: from m50-110.126.com ([123.125.50.110]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZgkRO-0003X1-Et; Tue, 29 Sep 2015 02:14:53 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=126.com; s=s110527; h=From:Subject:Date:Message-Id; bh=HyPGIZDiZ+Ug5pbTDe tlAUgUirx+Z70DhAJgC0d7flA=; b=VRg21sBSNBoxouZpkOwauk4JVuYa5i5HDV FGyUnbq1P8ZHpBQEgJc+/fln96IMT7iTPhPgEHVYpbcZF2tz/SKboMJimjeFPo4E 2Fyg4+IINdBgK56U5aFJPek8yZeZkxaAvsMYx9uFkd1vNxzk/Q+IUR1J0H7nts1T Nh+92w8jY= Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp4 (Coremail) with SMTP id jdKowAAHNTbm8wlWsm1UAw--.42159S6; Tue, 29 Sep 2015 10:14:04 +0800 (CST) From: Xing Zheng To: heiko@sntech.de Subject: [PATCH v3 4/8] dt-bindings: add documentation of rk3036 clock controller Date: Tue, 29 Sep 2015 10:13:49 +0800 Message-Id: <1443492833-15630-5-git-send-email-zhengxing@rock-chips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1443492833-15630-1-git-send-email-zhengxing@rock-chips.com> References: <1443492833-15630-1-git-send-email-zhengxing@rock-chips.com> X-CM-TRANSID: jdKowAAHNTbm8wlWsm1UAw--.42159S6 X-Coremail-Antispam: 1Uf129KBjvJXoWxXr1fJry3ury7ur4DAF1DZFb_yoW5GrWkpa n8G3y3JFs2vF1fuwsrK3WIyrs3J3WkCF4xXrZrJr1UJws8KryrKFW3Kry5ZasrGF1xZa9x ZF42kFy8Kwn2vaUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jwiSdUUUUU= X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: hdfj65a6rslhhfrp/1tbi7gyE-VWngCr8ZAABsa X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150928_191450_926085_CACD4159 X-CRM114-Status: GOOD ( 10.61 ) X-Spam-Score: -1.7 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Xing Zheng , Pawel Moll , Ian Campbell , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Rob Herring , Kumar Gala , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the devicetree binding for the cru on the rk3036 which quite similar structured as previous clock controllers. Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner --- Changes in v3: None .../bindings/clock/rockchip,rk3036-cru.txt | 56 ++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt new file mode 100644 index 0000000..ace0599 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt @@ -0,0 +1,56 @@ +* Rockchip RK3036 Clock and Reset Unit + +The RK3036 clock controller generates and supplies clock to various +controllers within the SoC and also implements a reset controller for SoC +peripherals. + +Required Properties: + +- compatible: should be "rockchip,rk3036-cru" +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Optional Properties: + +- rockchip,grf: phandle to the syscon managing the "general register files" + If missing pll rates are not changeable, due to the missing pll lock status. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be +used in device tree sources. Similar macros exist for the reset sources in +these files. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "xin24m" - crystal input - required, + - "ext_i2s" - external I2S clock - optional, + - "ext_gmac" - external GMAC clock - optional + +Example: Clock controller node: + + cru: cru@20000000 { + compatible = "rockchip,rk3036-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart0: serial@20060000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20060000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART0>; + };