From patchwork Tue Sep 29 20:44:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Balbi X-Patchwork-Id: 7290281 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 84107BEEA4 for ; Tue, 29 Sep 2015 20:55:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7E3FE20671 for ; Tue, 29 Sep 2015 20:55:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6E16A20670 for ; Tue, 29 Sep 2015 20:55:19 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zh1u7-0003PZ-B7; Tue, 29 Sep 2015 20:53:39 +0000 Received: from bear.ext.ti.com ([192.94.94.41]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zh1lW-0004Sv-JG for linux-arm-kernel@lists.infradead.org; Tue, 29 Sep 2015 20:44:48 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id t8TKiH51006013; Tue, 29 Sep 2015 15:44:17 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t8TKiHWd020547; Tue, 29 Sep 2015 15:44:17 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.224.2; Tue, 29 Sep 2015 15:44:18 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t8TKiGUb011975; Tue, 29 Sep 2015 15:44:17 -0500 From: Felipe Balbi To: Tony Lindgren Subject: [RFC/PATCH 09/11] clocksource: add TI 32.768 Hz counter driver Date: Tue, 29 Sep 2015 15:44:04 -0500 Message-ID: <1443559446-26969-10-git-send-email-balbi@ti.com> X-Mailer: git-send-email 2.5.3 In-Reply-To: <1443559446-26969-1-git-send-email-balbi@ti.com> References: <1443559446-26969-1-git-send-email-balbi@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150929_134446_850602_58531C29 X-CRM114-Status: GOOD ( 20.58 ) X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.lezcano@linaro.org, Linux Kernel Mailing List , Felipe Balbi , tglx@linutronix.de, Linux OMAP Mailing List , Linux ARM Kernel Mailing List Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce a new clocksource driver for Texas Instruments 32.768 Hz device which is available on most OMAP-like devices. Signed-off-by: Felipe Balbi --- drivers/clocksource/Kconfig | 8 +++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-ti-32k.c | 121 +++++++++++++++++++++++++++++++++++++ 3 files changed, 130 insertions(+) create mode 100644 drivers/clocksource/timer-ti-32k.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index a7726db13abb..0ccfd12a00a3 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -115,6 +115,14 @@ config CLKSRC_PISTACHIO bool select CLKSRC_OF +config CLKSRC_TI_32K + bool "Texas Instruments 32.768 Hz Clocksource" + depends on OF && ARCH_OMAP2PLUS + select CLKSRC_OF + help + This option enables support for Texas Instruments 32.768 Hz clocksource + available on many OMAP-like platforms. + config CLKSRC_STM32 bool "Clocksource for STM32 SoCs" if !ARCH_STM32 depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 5c00863c3e33..749abc3665b3 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o +obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o diff --git a/drivers/clocksource/timer-ti-32k.c b/drivers/clocksource/timer-ti-32k.c new file mode 100644 index 000000000000..10ccce2eb645 --- /dev/null +++ b/drivers/clocksource/timer-ti-32k.c @@ -0,0 +1,121 @@ +/** + * timer-ti-32k.c - OMAP2 32k Timer Support + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 of + * the License as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ +#define OMAP2_32KSYNCNT_REV_OFF 0x0 +#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30) +#define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10 +#define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30 + +/* + * 32KHz clocksource ... always available, on pretty most chips except + * OMAP 730 and 1510. Other timers could be used as clocksources, with + * higher resolution in free-running counter modes (e.g. 12 MHz xtal), + * but systems won't necessarily want to spend resources that way. + */ +static void __iomem *sync32k_cnt_reg; + +/** + * omap_read_persistent_clock64 - Return time from a persistent clock. + * + * Reads the time from a source which isn't disabled during PM, the + * 32k sync timer. Convert the cycles elapsed since last read into + * nsecs and adds to a monotonically increasing timespec64. + */ +static struct timespec64 persistent_ts; +static cycles_t cycles; +static unsigned int persistent_mult, persistent_shift; + +static u64 notrace omap_32k_read_sched_clock(void) +{ + return readl_relaxed(sync32k_cnt_reg); +} + +static void omap_read_persistent_clock64(struct timespec64 *ts) +{ + unsigned long long nsecs; + cycles_t last_cycles; + + last_cycles = cycles; + cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; + + nsecs = clocksource_cyc2ns(cycles - last_cycles, + persistent_mult, persistent_shift); + + timespec64_add_ns(&persistent_ts, nsecs); + + *ts = persistent_ts; +} + +static void __init ti_32k_timer_init(struct device_node *np) +{ + void __iomem *vbase; + int ret; + + vbase = of_iomap(np, 0); + if (!vbase) { + pr_err("Can't ioremap 32k timer base\n"); + return; + } + + /* + * 32k sync Counter IP register offsets vary between the + * highlander version and the legacy ones. + * The 'SCHEME' bits(30-31) of the revision register is used + * to identify the version. + */ + if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) & + OMAP2_32KSYNCNT_REV_SCHEME) + sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH; + else + sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW; + + /* + * 120000 rough estimate from the calculations in + * __clocksource_update_freq_scale. + */ + clocks_calc_mult_shift(&persistent_mult, &persistent_shift, + 32768, NSEC_PER_SEC, 120000); + + ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768, + 250, 32, clocksource_mmio_readl_up); + if (ret) { + pr_err("32k_counter: can't register clocksource\n"); + return; + } + + sched_clock_register(omap_32k_read_sched_clock, 32, 32768); + register_persistent_clock(NULL, omap_read_persistent_clock64); + pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n"); +} +CLOCKSOURCE_OF_DECLARE(ti_32k_timer, "ti,omap-counter32k", + ti_32k_timer_init);