From patchwork Tue Oct 13 21:07:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Mason X-Patchwork-Id: 7388791 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1F1F8BEEA4 for ; Tue, 13 Oct 2015 21:10:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D7B10207BE for ; Tue, 13 Oct 2015 21:10:41 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 778A1207CA for ; Tue, 13 Oct 2015 21:10:40 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zm6oT-0006Hx-Uz; Tue, 13 Oct 2015 21:08:49 +0000 Received: from mail-gw1-out.broadcom.com ([216.31.210.62]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zm6oJ-0006As-1R for linux-arm-kernel@lists.infradead.org; Tue, 13 Oct 2015 21:08:40 +0000 X-IronPort-AV: E=Sophos;i="5.17,680,1437462000"; d="scan'208";a="77614447" Received: from irvexchcas08.broadcom.com (HELO IRVEXCHCAS08.corp.ad.broadcom.com) ([10.9.208.57]) by mail-gw1-out.broadcom.com with ESMTP; 13 Oct 2015 16:01:03 -0700 Received: from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.3.235.1; Tue, 13 Oct 2015 14:08:17 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP Server id 14.3.235.1; Tue, 13 Oct 2015 14:08:16 -0700 Received: from venom.rtp.broadcom.com (unknown [10.27.64.103]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id C9F5440FE8; Tue, 13 Oct 2015 14:05:22 -0700 (PDT) From: Jon Mason To: Michael Turquette , Stephen Boyd Subject: [PATCH v2 1/7] clk: cygnus: Convert all macros to all caps Date: Tue, 13 Oct 2015 17:07:59 -0400 Message-ID: <1444770485-11210-2-git-send-email-jonmason@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444770485-11210-1-git-send-email-jonmason@broadcom.com> References: <1444770485-11210-1-git-send-email-jonmason@broadcom.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151013_140839_252179_24B6E8F5 X-CRM114-Status: UNSURE ( 9.79 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -4.2 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Florian Fainelli , Scott Branden , Hauke Mehrtens , linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, Ray Jui , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The macros that are being used to initialize the values of the clk structures should be all caps. Find and replace all of them with their relevant counterparts. Signed-off-by: Jon Mason --- drivers/clk/bcm/clk-cygnus.c | 146 +++++++++++++++++++++---------------------- 1 file changed, 73 insertions(+), 73 deletions(-) diff --git a/drivers/clk/bcm/clk-cygnus.c b/drivers/clk/bcm/clk-cygnus.c index 316c603..aac82c6 100644 --- a/drivers/clk/bcm/clk-cygnus.c +++ b/drivers/clk/bcm/clk-cygnus.c @@ -23,28 +23,28 @@ #include #include "clk-iproc.h" -#define reg_val(o, s, w) { .offset = o, .shift = s, .width = w, } +#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, } -#define aon_val(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ +#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ .pwr_shift = ps, .iso_shift = is } -#define sw_ctrl_val(o, s) { .offset = o, .shift = s, } +#define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, } -#define asiu_div_val(o, es, hs, hw, ls, lw) \ +#define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \ { .offset = o, .en_shift = es, .high_shift = hs, \ .high_width = hw, .low_shift = ls, .low_width = lw } -#define reset_val(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ +#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ .ka_width = kaw } -#define vco_ctrl_val(uo, lo) { .u_offset = uo, .l_offset = lo } +#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo } -#define enable_val(o, es, hs, bs) { .offset = o, .enable_shift = es, \ +#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ .hold_shift = hs, .bypass_shift = bs } -#define asiu_gate_val(o, es) { .offset = o, .en_shift = es } +#define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es } static void __init cygnus_armpll_init(struct device_node *node) { @@ -55,52 +55,52 @@ CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init); static const struct iproc_pll_ctrl genpll = { .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_PLL_NEEDS_SW_CFG, - .aon = aon_val(0x0, 2, 1, 0), - .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3), - .sw_ctrl = sw_ctrl_val(0x10, 31), - .ndiv_int = reg_val(0x10, 20, 10), - .ndiv_frac = reg_val(0x10, 0, 20), - .pdiv = reg_val(0x14, 0, 4), - .vco_ctrl = vco_ctrl_val(0x18, 0x1c), - .status = reg_val(0x28, 12, 1), + .aon = AON_VAL(0x0, 2, 1, 0), + .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), + .sw_ctrl = SW_CTRL_VAL(0x10, 31), + .ndiv_int = REG_VAL(0x10, 20, 10), + .ndiv_frac = REG_VAL(0x10, 0, 20), + .pdiv = REG_VAL(0x14, 0, 4), + .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c), + .status = REG_VAL(0x28, 12, 1), }; static const struct iproc_clk_ctrl genpll_clk[] = { [BCM_CYGNUS_GENPLL_AXI21_CLK] = { .channel = BCM_CYGNUS_GENPLL_AXI21_CLK, .flags = IPROC_CLK_AON, - .enable = enable_val(0x4, 6, 0, 12), - .mdiv = reg_val(0x20, 0, 8), + .enable = ENABLE_VAL(0x4, 6, 0, 12), + .mdiv = REG_VAL(0x20, 0, 8), }, [BCM_CYGNUS_GENPLL_250MHZ_CLK] = { .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK, .flags = IPROC_CLK_AON, - .enable = enable_val(0x4, 7, 1, 13), - .mdiv = reg_val(0x20, 10, 8), + .enable = ENABLE_VAL(0x4, 7, 1, 13), + .mdiv = REG_VAL(0x20, 10, 8), }, [BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = { .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK, .flags = IPROC_CLK_AON, - .enable = enable_val(0x4, 8, 2, 14), - .mdiv = reg_val(0x20, 20, 8), + .enable = ENABLE_VAL(0x4, 8, 2, 14), + .mdiv = REG_VAL(0x20, 20, 8), }, [BCM_CYGNUS_GENPLL_ENET_SW_CLK] = { .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK, .flags = IPROC_CLK_AON, - .enable = enable_val(0x4, 9, 3, 15), - .mdiv = reg_val(0x24, 0, 8), + .enable = ENABLE_VAL(0x4, 9, 3, 15), + .mdiv = REG_VAL(0x24, 0, 8), }, [BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = { .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK, .flags = IPROC_CLK_AON, - .enable = enable_val(0x4, 10, 4, 16), - .mdiv = reg_val(0x24, 10, 8), + .enable = ENABLE_VAL(0x4, 10, 4, 16), + .mdiv = REG_VAL(0x24, 10, 8), }, [BCM_CYGNUS_GENPLL_CAN_CLK] = { .channel = BCM_CYGNUS_GENPLL_CAN_CLK, .flags = IPROC_CLK_AON, - .enable = enable_val(0x4, 11, 5, 17), - .mdiv = reg_val(0x24, 20, 8), + .enable = ENABLE_VAL(0x4, 11, 5, 17), + .mdiv = REG_VAL(0x24, 20, 8), }, }; @@ -113,51 +113,51 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init); static const struct iproc_pll_ctrl lcpll0 = { .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG, - .aon = aon_val(0x0, 2, 5, 4), - .reset = reset_val(0x0, 31, 30, 27, 3, 23, 4, 19, 4), - .sw_ctrl = sw_ctrl_val(0x4, 31), - .ndiv_int = reg_val(0x4, 16, 10), - .pdiv = reg_val(0x4, 26, 4), - .vco_ctrl = vco_ctrl_val(0x10, 0x14), - .status = reg_val(0x18, 12, 1), + .aon = AON_VAL(0x0, 2, 5, 4), + .reset = RESET_VAL(0x0, 31, 30, 27, 3, 23, 4, 19, 4), + .sw_ctrl = SW_CTRL_VAL(0x4, 31), + .ndiv_int = REG_VAL(0x4, 16, 10), + .pdiv = REG_VAL(0x4, 26, 4), + .vco_ctrl = VCO_CTRL_VAL(0x10, 0x14), + .status = REG_VAL(0x18, 12, 1), }; static const struct iproc_clk_ctrl lcpll0_clk[] = { [BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK] = { .channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK, .flags = IPROC_CLK_AON, - .enable = enable_val(0x0, 7, 1, 13), - .mdiv = reg_val(0x8, 0, 8), + .enable = ENABLE_VAL(0x0, 7, 1, 13), + .mdiv = REG_VAL(0x8, 0, 8), }, [BCM_CYGNUS_LCPLL0_DDR_PHY_CLK] = { .channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK, .flags = IPROC_CLK_AON, - .enable = enable_val(0x0, 8, 2, 14), - .mdiv = reg_val(0x8, 10, 8), + .enable = ENABLE_VAL(0x0, 8, 2, 14), + .mdiv = REG_VAL(0x8, 10, 8), }, [BCM_CYGNUS_LCPLL0_SDIO_CLK] = { .channel = BCM_CYGNUS_LCPLL0_SDIO_CLK, .flags = IPROC_CLK_AON, - .enable = enable_val(0x0, 9, 3, 15), - .mdiv = reg_val(0x8, 20, 8), + .enable = ENABLE_VAL(0x0, 9, 3, 15), + .mdiv = REG_VAL(0x8, 20, 8), }, [BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK] = { .channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK, .flags = IPROC_CLK_AON, - .enable = enable_val(0x0, 10, 4, 16), - .mdiv = reg_val(0xc, 0, 8), + .enable = ENABLE_VAL(0x0, 10, 4, 16), + .mdiv = REG_VAL(0xc, 0, 8), }, [BCM_CYGNUS_LCPLL0_SMART_CARD_CLK] = { .channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK, .flags = IPROC_CLK_AON, - .enable = enable_val(0x0, 11, 5, 17), - .mdiv = reg_val(0xc, 10, 8), + .enable = ENABLE_VAL(0x0, 11, 5, 17), + .mdiv = REG_VAL(0xc, 10, 8), }, [BCM_CYGNUS_LCPLL0_CH5_UNUSED] = { .channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED, .flags = IPROC_CLK_AON, - .enable = enable_val(0x0, 12, 6, 18), - .mdiv = reg_val(0xc, 20, 8), + .enable = ENABLE_VAL(0x0, 12, 6, 18), + .mdiv = REG_VAL(0xc, 20, 8), }, }; @@ -189,52 +189,52 @@ static const struct iproc_pll_vco_param mipipll_vco_params[] = { static const struct iproc_pll_ctrl mipipll = { .flags = IPROC_CLK_PLL_ASIU | IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_NEEDS_READ_BACK, - .aon = aon_val(0x0, 4, 17, 16), - .asiu = asiu_gate_val(0x0, 3), - .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 4), - .ndiv_int = reg_val(0x10, 20, 10), - .ndiv_frac = reg_val(0x10, 0, 20), - .pdiv = reg_val(0x14, 0, 4), - .vco_ctrl = vco_ctrl_val(0x18, 0x1c), - .status = reg_val(0x28, 12, 1), + .aon = AON_VAL(0x0, 4, 17, 16), + .asiu = ASIU_GATE_VAL(0x0, 3), + .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4), + .ndiv_int = REG_VAL(0x10, 20, 10), + .ndiv_frac = REG_VAL(0x10, 0, 20), + .pdiv = REG_VAL(0x14, 0, 4), + .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c), + .status = REG_VAL(0x28, 12, 1), }; static const struct iproc_clk_ctrl mipipll_clk[] = { [BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = { .channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED, .flags = IPROC_CLK_NEEDS_READ_BACK, - .enable = enable_val(0x4, 12, 6, 18), - .mdiv = reg_val(0x20, 0, 8), + .enable = ENABLE_VAL(0x4, 12, 6, 18), + .mdiv = REG_VAL(0x20, 0, 8), }, [BCM_CYGNUS_MIPIPLL_CH1_LCD] = { .channel = BCM_CYGNUS_MIPIPLL_CH1_LCD, .flags = IPROC_CLK_NEEDS_READ_BACK, - .enable = enable_val(0x4, 13, 7, 19), - .mdiv = reg_val(0x20, 10, 8), + .enable = ENABLE_VAL(0x4, 13, 7, 19), + .mdiv = REG_VAL(0x20, 10, 8), }, [BCM_CYGNUS_MIPIPLL_CH2_V3D] = { .channel = BCM_CYGNUS_MIPIPLL_CH2_V3D, .flags = IPROC_CLK_NEEDS_READ_BACK, - .enable = enable_val(0x4, 14, 8, 20), - .mdiv = reg_val(0x20, 20, 8), + .enable = ENABLE_VAL(0x4, 14, 8, 20), + .mdiv = REG_VAL(0x20, 20, 8), }, [BCM_CYGNUS_MIPIPLL_CH3_UNUSED] = { .channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED, .flags = IPROC_CLK_NEEDS_READ_BACK, - .enable = enable_val(0x4, 15, 9, 21), - .mdiv = reg_val(0x24, 0, 8), + .enable = ENABLE_VAL(0x4, 15, 9, 21), + .mdiv = REG_VAL(0x24, 0, 8), }, [BCM_CYGNUS_MIPIPLL_CH4_UNUSED] = { .channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED, .flags = IPROC_CLK_NEEDS_READ_BACK, - .enable = enable_val(0x4, 16, 10, 22), - .mdiv = reg_val(0x24, 10, 8), + .enable = ENABLE_VAL(0x4, 16, 10, 22), + .mdiv = REG_VAL(0x24, 10, 8), }, [BCM_CYGNUS_MIPIPLL_CH5_UNUSED] = { .channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED, .flags = IPROC_CLK_NEEDS_READ_BACK, - .enable = enable_val(0x4, 17, 11, 23), - .mdiv = reg_val(0x24, 20, 8), + .enable = ENABLE_VAL(0x4, 17, 11, 23), + .mdiv = REG_VAL(0x24, 20, 8), }, }; @@ -247,15 +247,15 @@ static void __init cygnus_mipipll_clk_init(struct device_node *node) CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init); static const struct iproc_asiu_div asiu_div[] = { - [BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_div_val(0x0, 31, 16, 10, 0, 10), - [BCM_CYGNUS_ASIU_ADC_CLK] = asiu_div_val(0x4, 31, 16, 10, 0, 10), - [BCM_CYGNUS_ASIU_PWM_CLK] = asiu_div_val(0x8, 31, 16, 10, 0, 10), + [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_DIV_VAL(0x0, 31, 16, 10, 0, 10), + [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_DIV_VAL(0x4, 31, 16, 10, 0, 10), + [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_DIV_VAL(0x8, 31, 16, 10, 0, 10), }; static const struct iproc_asiu_gate asiu_gate[] = { - [BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_gate_val(0x0, 7), - [BCM_CYGNUS_ASIU_ADC_CLK] = asiu_gate_val(0x0, 9), - [BCM_CYGNUS_ASIU_PWM_CLK] = asiu_gate_val(IPROC_CLK_INVALID_OFFSET, 0), + [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_GATE_VAL(0x0, 7), + [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_GATE_VAL(0x0, 9), + [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_GATE_VAL(IPROC_CLK_INVALID_OFFSET, 0), }; static void __init cygnus_asiu_init(struct device_node *node)