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Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BY2FFO11FD004.mail.protection.outlook.com (10.1.14.158) with Microsoft SMTP Server (TLS) id 15.1.293.9 via Frontend Transport; Thu, 15 Oct 2015 07:04:02 +0000 Received: from localhost.localdomain ([10.214.249.140]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t9F726js013518; Thu, 15 Oct 2015 00:03:55 -0700 From: Bhupesh Sharma To: , , , , , Subject: [PATCH v3 04/12] Documentation/dts: Move FSL board-specific bindings out of /powerpc Date: Thu, 15 Oct 2015 12:17:44 +0530 Message-ID: <1444891672-32117-5-git-send-email-bhupesh.sharma@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1444891672-32117-1-git-send-email-bhupesh.sharma@freescale.com> References: <1444891672-32117-1-git-send-email-bhupesh.sharma@freescale.com> X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; 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While at it, this patch also adds the bindings for QIXIS FPGA controller found on FSL LS2080A boards. These boards have an on-board FPGA/CPLD connected to the IFC controller. Signed-off-by: Bhupesh Sharma Signed-off-by: Jaiprakash Singh --- .../{powerpc/fsl/board.txt => board/fsl-board.txt} | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) rename Documentation/devicetree/bindings/{powerpc/fsl/board.txt => board/fsl-board.txt} (90%) diff --git a/Documentation/devicetree/bindings/powerpc/fsl/board.txt b/Documentation/devicetree/bindings/board/fsl-board.txt similarity index 90% rename from Documentation/devicetree/bindings/powerpc/fsl/board.txt rename to Documentation/devicetree/bindings/board/fsl-board.txt index cff38bd..fb7b03e 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/board.txt +++ b/Documentation/devicetree/bindings/board/fsl-board.txt @@ -21,11 +21,14 @@ Example: This is the memory-mapped registers for on board FPGA. -Required properities: +Required properties: - compatible: should be a board-specific string followed by a string indicating the type of FPGA. Example: - "fsl,-fpga", "fsl,fpga-pixis" + "fsl,-fpga", "fsl,fpga-pixis", or + "fsl,-fpga", "fsl,fpga-qixis" - reg: should contain the address and the length of the FPGA register set. + +Optional properties: - interrupt-parent: should specify phandle for the interrupt controller. - interrupts: should specify event (wakeup) IRQ. @@ -38,6 +41,13 @@ Example (P1022DS): interrupts = <8 8 0 0>; }; +Example (LS2080A-RDB): + + cpld@3,0 { + compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis"; + reg = <0x3 0 0x10000>; + }; + * Freescale BCSR GPIO banks Some BCSR registers act as simple GPIO controllers, each such