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[PATCHv2,1/3] ARM: dt: fpga: Added binding docs for Xilinx Zynq FPGA manager.

Message ID 1445035350-3569-2-git-send-email-moritz.fischer@ettus.com (mailing list archive)
State New, archived
Headers show

Commit Message

Moritz Fischer Oct. 16, 2015, 10:42 p.m. UTC
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
---

v2:
 - Clock names are now a required property
 - Removed interrupt-parent property

---
 .../devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt

Comments

Josh Cartwright Oct. 18, 2015, 5:51 p.m. UTC | #1
On Fri, Oct 16, 2015 at 03:42:28PM -0700, Moritz Fischer wrote:
> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
> ---
> 
> v2:
>  - Clock names are now a required property
>  - Removed interrupt-parent property
> 
> ---
>  .../devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
> 
> diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
> new file mode 100644
> index 0000000..7018aa8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
> @@ -0,0 +1,19 @@
> +Xilinx Zynq FPGA Manager
> +
> +Required properties:
> +- compatible:		should contain "xlnx,zynq-devcfg-1.0"
> +- reg:			base address and size for memory mapped io
> +- interrupts:		interrupt for the FPGA manager device
> +- clocks:		phandle for clocks required operation

Technically a "clock specifier", but other than that:

Reviewed-by: Josh Cartwright <joshc@ni.com>

  Josh
Soren Brinkmann Oct. 19, 2015, 2:24 a.m. UTC | #2
On Sun, 2015-10-18 at 12:51PM -0500, Josh Cartwright wrote:
> On Fri, Oct 16, 2015 at 03:42:28PM -0700, Moritz Fischer wrote:
> > Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
> > ---
> > 
> > v2:
> >  - Clock names are now a required property
> >  - Removed interrupt-parent property
> > 
> > ---
> >  .../devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt | 19 +++++++++++++++++++
> >  1 file changed, 19 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
> > new file mode 100644
> > index 0000000..7018aa8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
> > @@ -0,0 +1,19 @@
> > +Xilinx Zynq FPGA Manager
> > +
> > +Required properties:
> > +- compatible:		should contain "xlnx,zynq-devcfg-1.0"
> > +- reg:			base address and size for memory mapped io
> > +- interrupts:		interrupt for the FPGA manager device

If we are that picky, this is technically an interrupt specifier :)

> > +- clocks:		phandle for clocks required operation
> 
> Technically a "clock specifier", but other than that:
> 
> Reviewed-by: Josh Cartwright <joshc@ni.com>
Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com>

	Sören
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
new file mode 100644
index 0000000..7018aa8
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
@@ -0,0 +1,19 @@ 
+Xilinx Zynq FPGA Manager
+
+Required properties:
+- compatible:		should contain "xlnx,zynq-devcfg-1.0"
+- reg:			base address and size for memory mapped io
+- interrupts:		interrupt for the FPGA manager device
+- clocks:		phandle for clocks required operation
+- clock-names:		name for the clock, should be "ref_clk"
+- syscon:		phandle for access to SLCR registers
+
+Example:
+	devcfg: devcfg@f8007000 {
+		compatible = "xlnx,zynq-devcfg-1.0";
+		reg = <0xf8007000 0x100>;
+		interrupts = <0 8 4>;
+		clocks = <&clkc 12>;
+		clock-names = "ref_clk";
+		syscon = <&slcr>;
+	};