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Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BL2FFO11FD035.mail.protection.outlook.com (10.173.161.131) with Microsoft SMTP Server (TLS) id 15.1.306.13 via Frontend Transport; Fri, 23 Oct 2015 02:05:48 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id t9N25g8W018012; Thu, 22 Oct 2015 19:05:45 -0700 From: Yuan Yao To: , Subject: [PATCH v2 2/3] dma: Binding for freescale qDMA engine driver support Date: Fri, 23 Oct 2015 09:59:12 +0800 Message-ID: <1445565553-1141-2-git-send-email-yao.yuan@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 In-Reply-To: <1445565553-1141-1-git-send-email-yao.yuan@freescale.com> References: <1445565553-1141-1-git-send-email-yao.yuan@freescale.com> X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; 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This module can be found on LS-1 and LS-2 SoCs. Signed-off-by: Yuan Yao --- Documentation/devicetree/bindings/dma/fsl-qdma.txt | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt new file mode 100644 index 0000000..cdae71c --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt @@ -0,0 +1,43 @@ +* Freescale queue Direct Memory Access Controller(qDMA) Controller + + The qDMA controller transfers blocks of data between one source and one or more +destinations. The blocks of data transferred can be represented in memory as contiguous +or non-contiguous using scatter/gather table(s). Channel virtualization is supported +through enqueuing of DMA jobs to, or dequeuing DMA jobs from, different work +queues. + Legacy mode is primarily included for software requiring the earlier +QorIQ DMA programming model. This mode provides a simple programming +model not utilizing the datapath architecture. In legacy mode, DMA +operations are directly configured through a set of architectural +registers per channel. + +* qDMA Controller +Required properties: +- compatible : + - "fsl,ls1021a-qdma" for qDMA used similar to that on LS SoC +- reg : Specifies base physical address(s) and size of the qDMA registers. + The region is qDMA control register's address and size. +- interrupts : A list of interrupt-specifiers, one for each entry in + interrupt-names. +- interrupt-names : Should contain: + "qdma-tx" - the interrupt + "qdma-err" - the error interrupt +- channels : Number of channels supported by the controller + +Optional properties: +- big-endian: If present registers and hardware scatter/gather descriptors + of the qDMA are implemented in big endian mode, otherwise in little + mode. + + +Examples: + + qdma: qdma@8390000 { + compatible = "fsl,ls1021a-qdma"; + reg = <0x0 0x8380000 0x0 0x20000>; + interrupts = , + ; + interrupt-names = "qdma-tx", "qdma-err"; + big-endian; + channels = <1>; + };