From patchwork Sat Oct 24 10:51:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhengxing X-Patchwork-Id: 7480151 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AAF2EBEEA4 for ; Sat, 24 Oct 2015 10:54:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C8261208E5 for ; Sat, 24 Oct 2015 10:53:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D5280208E4 for ; Sat, 24 Oct 2015 10:53:58 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZpwR9-0004ns-Dt; Sat, 24 Oct 2015 10:52:35 +0000 Received: from regular1.263xmail.com ([211.150.99.130]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZpwR3-0004hZ-3l; Sat, 24 Oct 2015 10:52:33 +0000 Received: from zhengxing?rock-chips.com (unknown [192.168.167.192]) by regular1.263xmail.com (Postfix) with SMTP id CBCC28417; Sat, 24 Oct 2015 18:51:57 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 068C31EAE5; Sat, 24 Oct 2015 18:51:50 +0800 (CST) X-RL-SENDER: zhengxing@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zhengxing@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: zhengxing@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 30071YV3DKG; Sat, 24 Oct 2015 18:51:51 +0800 (CST) From: Xing Zheng To: heiko@sntech.de Subject: [PATCH v4 8/8] rockchip: make sure timer5 is enabled on rk3036 platforms Date: Sat, 24 Oct 2015 18:51:55 +0800 Message-Id: <1445683915-21913-1-git-send-email-zhengxing@rock-chips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1445682629-21632-1-git-send-email-zhengxing@rock-chips.com> References: <1445682629-21632-1-git-send-email-zhengxing@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151024_035232_493811_C79AAB09 X-CRM114-Status: UNSURE ( 9.73 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, Xing Zheng , linux@arm.linux.org.uk, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD,UNPARSEABLE_RELAY,URIBL_BLACK autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The timer5 supplies the architected timer and thus as has to run when the system clocksource and clockevents drivers are registered. --- Changes in v4: Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner arch/arm/mach-rockchip/rockchip.c | 44 +++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index 251c7b9..608b31c 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -29,31 +29,38 @@ #include "core.h" #include "pm.h" +#define RK3036_TIMER_PHYS 0x20044000 + #define RK3288_GRF_SOC_CON0 0x244 #define RK3288_TIMER6_7_PHYS 0xff810000 +static void rockchip_init_arch_timer_supply(resource_size_t phys, int offs) +{ + void __iomem *reg_base = ioremap(phys, SZ_16K); + + /* + * Most/all uboot versions for Rockchip SoCs don't enable + * timer which is needed for the architected timer to work. + * So make sure it is running during early boot. + */ + if (reg_base) { + writel(0, reg_base + offs + 0x10); + writel(0xffffffff, reg_base + offs); + writel(0xffffffff, reg_base + offs + 0x04); + writel(1, reg_base + offs + 0x10); + dsb(); + iounmap(reg_base); + } else { + pr_err("rockchip: could not map timer registers\n"); + } +} + static void __init rockchip_timer_init(void) { if (of_machine_is_compatible("rockchip,rk3288")) { struct regmap *grf; - void __iomem *reg_base; - /* - * Most/all uboot versions for rk3288 don't enable timer7 - * which is needed for the architected timer to work. - * So make sure it is running during early boot. - */ - reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K); - if (reg_base) { - writel(0, reg_base + 0x30); - writel(0xffffffff, reg_base + 0x20); - writel(0xffffffff, reg_base + 0x24); - writel(1, reg_base + 0x30); - dsb(); - iounmap(reg_base); - } else { - pr_err("rockchip: could not map timer7 registers\n"); - } + rockchip_init_arch_timer_supply(RK3288_TIMER6_7_PHYS, 0x20); /* * Disable auto jtag/sdmmc switching that causes issues @@ -64,6 +71,8 @@ static void __init rockchip_timer_init(void) regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000); else pr_err("rockchip: could not get grf syscon\n"); + } else if (of_machine_is_compatible("rockchip,rk3036")) { + rockchip_init_arch_timer_supply(RK3036_TIMER_PHYS, 0xa0); } of_clk_init(NULL); @@ -79,6 +88,7 @@ static void __init rockchip_dt_init(void) static const char * const rockchip_board_dt_compat[] = { "rockchip,rk2928", + "rockchip,rk3036", "rockchip,rk3066a", "rockchip,rk3066b", "rockchip,rk3188",