From patchwork Mon Oct 26 21:32:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Olliver Schinagl X-Patchwork-Id: 7492221 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D85349F327 for ; Mon, 26 Oct 2015 21:36:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0AC9C20461 for ; Mon, 26 Oct 2015 21:36:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3C4D72042B for ; Mon, 26 Oct 2015 21:35:59 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZqpPU-0002lM-L9; Mon, 26 Oct 2015 21:34:32 +0000 Received: from 7of9.schinagl.nl ([88.159.158.68]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZqpOg-0001c3-Lb for linux-arm-kernel@lists.infradead.org; Mon, 26 Oct 2015 21:33:48 +0000 Received: from um-mba-140.are-b.org. (unknown [10.2.0.189]) by 7of9.schinagl.nl (Postfix) with ESMTPA id 71DD84466C; Mon, 26 Oct 2015 22:32:54 +0100 (CET) From: Olliver Schinagl To: Olliver Schinagl , Thierry Reding , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Joachim Eastwood , Maxime Ripard , Alexandre Belloni Subject: [PATCH 10/10] pwm: sunxi: Add possibility to pulse the sunxi pwm output Date: Mon, 26 Oct 2015 22:32:41 +0100 Message-Id: <1445895161-2317-11-git-send-email-o.schinagl@ultimaker.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1445895161-2317-1-git-send-email-o.schinagl@ultimaker.com> References: <1445895161-2317-1-git-send-email-o.schinagl@ultimaker.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151026_143343_292406_0AB3E372 X-CRM114-Status: GOOD ( 11.89 ) X-Spam-Score: -1.2 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Olliver Schinagl , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Olliver Schinagl With the new pulse mode addition to the PWM framework, we can make use of this for the sunxi PWM. WARNING: Do not merge yet, currently, we can only pulse once and a manual disable is required to 'reset' the PWM framework. I haven't thought through how to automatically 'disable' the PWM after the pulse is finished and need some guidance here. Signed-off-by: Olliver Schinagl --- drivers/pwm/pwm-sun4i.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 6347ca8..8370cca 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -32,7 +32,7 @@ #define PWM_EN BIT(4) #define PWM_ACT_STATE BIT(5) #define PWM_CLK_GATING BIT(6) -#define PWM_MODE BIT(7) +#define PWM_MODE_PULSE BIT(7) #define PWM_PULSE BIT(8) #define PWM_BYPASS BIT(9) @@ -166,6 +166,8 @@ static int sun4i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, spin_lock(&sun4i_pwm->ctrl_lock); val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); + if (pulse_count) + val |= BIT_CH(PWM_MODE_PULSE, pwm->hwpwm); if (sun4i_pwm->data->has_rdy && (val & PWM_RDY(pwm->hwpwm))) { ret = -EBUSY; goto out; @@ -237,7 +239,10 @@ static int sun4i_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) spin_lock(&sun4i_pwm->ctrl_lock); val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); - val |= BIT_CH(PWM_EN, pwm->hwpwm); + if (pwm->pulse_count) + val |= BIT_CH(PWM_PULSE, pwm->hwpwm); + else + val |= BIT_CH(PWM_EN, pwm->hwpwm); val |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG); spin_unlock(&sun4i_pwm->ctrl_lock); @@ -350,9 +355,12 @@ static int sun4i_pwm_probe(struct platform_device *pdev) } val = sun4i_pwm_readl(pwm, PWM_CTRL_REG); - for (i = 0; i < pwm->chip.npwm; i++) + for (i = 0; i < pwm->chip.npwm; i++) { if (!(val & BIT_CH(PWM_ACT_STATE, i))) pwm->chip.pwms[i].polarity = PWM_POLARITY_INVERSED; + + pwm_set_pulse_count_max(&pwm->chip.pwms[i], 1); + } clk_disable_unprepare(pwm->clk); return 0;