From patchwork Wed Oct 28 21:43:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Van Brunt X-Patchwork-Id: 7514301 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BE8D49F2F7 for ; Wed, 28 Oct 2015 21:46:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E376B205CD for ; Wed, 28 Oct 2015 21:46:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1542C20461 for ; Wed, 28 Oct 2015 21:46:15 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZrYWT-000653-4A; Wed, 28 Oct 2015 21:44:45 +0000 Received: from merlin.infradead.org ([2001:4978:20e::2]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZrYVn-0005md-KN for linux-arm-kernel@bombadil.infradead.org; Wed, 28 Oct 2015 21:44:03 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by merlin.infradead.org with esmtps (Exim 4.85 #2 (Red Hat Linux)) id 1ZrYVm-0002KB-CG for linux-arm-kernel@lists.infradead.org; Wed, 28 Oct 2015 21:44:02 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Wed, 28 Oct 2015 14:43:35 -0700 Received: from hqemhub03.nvidia.com ([172.20.150.15]) by hqnvupgp07.nvidia.com (PGP Universal service); Wed, 28 Oct 2015 14:33:47 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 28 Oct 2015 14:33:47 -0700 Received: from avanbrunt-dt.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.342.0; Wed, 28 Oct 2015 14:43:27 -0700 From: Alex Van Brunt To: linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Will Deacon , Sudeep Holla , Catalin Marinas Subject: [PATCH 3/3] Revert "arm64: add helper functions to read I-cache attributes" Date: Wed, 28 Oct 2015 14:43:57 -0700 Message-ID: <1446068637-11509-4-git-send-email-avanbrunt@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1446068637-11509-1-git-send-email-avanbrunt@nvidia.com> References: <1446068637-11509-1-git-send-email-avanbrunt@nvidia.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151028_174402_487963_856D127F X-CRM114-Status: UNSURE ( 9.96 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Van Brunt Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This reverts commit 80c517b0ff71a4c874fed9196fd990d2d9e911f3. Signed-off-by: Alex Van Brunt --- arch/arm64/include/asm/cachetype.h | 20 -------------------- arch/arm64/kernel/cpuinfo.c | 14 -------------- 2 files changed, 34 deletions(-) diff --git a/arch/arm64/include/asm/cachetype.h b/arch/arm64/include/asm/cachetype.h index 4c631a0..7a2e076 100644 --- a/arch/arm64/include/asm/cachetype.h +++ b/arch/arm64/include/asm/cachetype.h @@ -39,26 +39,6 @@ extern unsigned long __icache_flags; -#define CCSIDR_EL1_LINESIZE_MASK 0x7 -#define CCSIDR_EL1_LINESIZE(x) ((x) & CCSIDR_EL1_LINESIZE_MASK) - -#define CCSIDR_EL1_NUMSETS_SHIFT 13 -#define CCSIDR_EL1_NUMSETS_MASK (0x7fff << CCSIDR_EL1_NUMSETS_SHIFT) -#define CCSIDR_EL1_NUMSETS(x) \ - (((x) & CCSIDR_EL1_NUMSETS_MASK) >> CCSIDR_EL1_NUMSETS_SHIFT) - -extern u64 __attribute_const__ icache_get_ccsidr(void); - -static inline int icache_get_linesize(void) -{ - return 16 << CCSIDR_EL1_LINESIZE(icache_get_ccsidr()); -} - -static inline int icache_get_numsets(void) -{ - return 1 + CCSIDR_EL1_NUMSETS(icache_get_ccsidr()); -} - /* * Whilst the D-side always behaves as PIPT on AArch64, aliasing is * permitted in the I-cache. diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index e0c6c8c..ae04ac1 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -21,10 +21,8 @@ #include #include -#include #include #include -#include #include #include @@ -244,15 +242,3 @@ void __init cpuinfo_store_boot_cpu(void) boot_cpu_data = *info; } - -u64 __attribute_const__ icache_get_ccsidr(void) -{ - u64 ccsidr; - - WARN_ON(preemptible()); - - /* Select L1 I-cache and read its size ID register */ - asm("msr csselr_el1, %1; isb; mrs %0, ccsidr_el1" - : "=r"(ccsidr) : "r"(1L)); - return ccsidr; -}