From patchwork Thu Oct 29 23:20:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Van Brunt X-Patchwork-Id: 7522111 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AE18A9F750 for ; Thu, 29 Oct 2015 23:23:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CE4482088F for ; Thu, 29 Oct 2015 23:23:38 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8310D20879 for ; Thu, 29 Oct 2015 23:23:37 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZrwW0-0005II-OU; Thu, 29 Oct 2015 23:21:52 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZrwTv-0002Hd-V1 for linux-arm-kernel@lists.infradead.org; Thu, 29 Oct 2015 23:19:46 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Thu, 29 Oct 2015 16:19:23 -0700 Received: from hqemhub03.nvidia.com ([172.20.150.15]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 29 Oct 2015 16:09:37 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 29 Oct 2015 16:09:37 -0700 Received: from avanbrunt-dt.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.342.0; Thu, 29 Oct 2015 16:19:23 -0700 From: Alex Van Brunt To: linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Will Deacon , Sudeep Holla , Catalin Marinas Subject: [PATCH v2 2/4] Revert "arm64: don't flag non-aliasing VIPT I-caches as aliasing" Date: Thu, 29 Oct 2015 16:20:40 -0700 Message-ID: <1446160842-25787-2-git-send-email-avanbrunt@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1446160842-25787-1-git-send-email-avanbrunt@nvidia.com> References: <1446160842-25787-1-git-send-email-avanbrunt@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151029_161944_179309_6374DFD3 X-CRM114-Status: GOOD ( 15.34 ) X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Van Brunt , stable@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This reverts commit 169c018de7b6d376f821f9fae0ab23dc5c7bb549. The reverted commit attempted to use the cache geometry as reported in CCSIDR to determine if there can be aliasing in the instruction cache. There were two problems with this: 1. CCSIDR_EL1 does not report the actual cache geometry. The architectural documentation for this register says: The parameters NumSets, Associativity, and LineSize in these registers define the architecturally visible parameters that are required for the cache maintenance by Set/Way instructions. They are not guaranteed to represent the actual microarchitectural features of a design. You cannot make any inference about the actual sizes of caches based on these parameters. 2. The architectural definition of VIPT and PIPT as reported by CTR_EL0 is described in terms of the observable behavior rather than the inner workings of the cache hardware. The difference in the definition of VIPT and PIPT is that VIPT requires invalidating the entire instruction cache to avoid aliasing. Therefore, even if the cache geometry was known, it is not possible to assume that there is no aliasing. Signed-off-by: Alex Van Brunt Cc: --- arch/arm64/kernel/cpuinfo.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 540177a..e0c6c8c 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -51,18 +51,8 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) unsigned int cpu = smp_processor_id(); u32 l1ip = CTR_L1IP(info->reg_ctr); - if (l1ip != ICACHE_POLICY_PIPT) { - /* - * VIPT caches are non-aliasing if the VA always equals the PA - * in all bit positions that are covered by the index. This is - * the case if the size of a way (# of sets * line size) does - * not exceed PAGE_SIZE. - */ - u32 waysize = icache_get_numsets() * icache_get_linesize(); - - if (l1ip != ICACHE_POLICY_VIPT || waysize > PAGE_SIZE) - set_bit(ICACHEF_ALIASING, &__icache_flags); - } + if (l1ip != ICACHE_POLICY_PIPT) + set_bit(ICACHEF_ALIASING, &__icache_flags); if (l1ip == ICACHE_POLICY_AIVIVT) set_bit(ICACHEF_AIVIVT, &__icache_flags);